- Capgemini (San Francisco, CA)
- ** RTL Design Engineer ** **Location: San Jose CA / Bay Area, but will consider remote.** **Job description:** . As an RTL Design Engineer you will ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic… more
- Google (Mountain View, CA)
- FPGA Design Engineer , Taara Hardware Engineering Mountain View, CA About the team: Project Taarafocuses on delivering high-throughput and long-range connectivity ... feedback-based precision line-of-sight tracking systems. + Develop testbenches for RTL modules, perform simulation, and verify design ...for RTL modules, perform simulation, and verify design requirements are met. + Integrate third party IP… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.… more
- Microsoft Corporation (Mountain View, CA)
- …cloud servers, clients, and augmented reality. We are looking for a **Senior** **Silicon** ** Design Engineer ** to work on leading edge custom IP development as ... responsible for leading the microarchitecture and Register Transfer Level ( RTL ) implementation of custom IP blocks, working with a...custom IP blocks, working with a group of other design team members, design verification engineers, and… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... Processing Unit (CPU) front-end designs, emphasizing micro-architecture and Register Transfer Level ( RTL ) design for the next generation CPU. + Propose… more
- Microsoft Corporation (Mountain View, CA)
- …cloud servers, clients, and augmented reality. We are looking for a Principal SOC Design Engineer to work in the dynamic Microsoft Artificial Intelligence System ... everyone can thrive at work and beyond. We are looking for a **Principal SoC Design Engineer ** to join our team! **Responsibilities** + Contribute to the SoC … more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... development, executing from the inception of the design ( RTL or gate netlist) through the...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Google (Mountain View, CA)
- …computer architecture concepts, including microarchitecture, multimedia architecture, and silicon design . Preferred qualifications: + Master's degree or Phd in ... learning accelerators). + Experience in ASIC development methodology and require Verilog RTL development as per the project demands. + Experience in collaborating,… more
- Google (Mountain View, CA)
- …using SystemVerilog for ASIC designs. + Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments. Preferred ... qualifications: + Experience in creating detailed block-level design verification strategies and plans. + Experience creating or...environments in methodology (UVM, VMM, OVM). + Experience in RTL , low power (eg, Unified Power Format or Common… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip… more
- Microsoft Corporation (Mountain View, CA)
- …customers and partners worldwide and we are looking for a **Principal Logic Engineer ** to help achieve that mission. As Microsoft's cloud business continues to grow, ... cloud hardware. We are looking for a **Principal Logic Engineer ** for customer focused solutions, insight and industry knowledge...blocks of a DRAM Memory Controller and implement the design with high quality in Verilog Register Transfer Level… more
- quadric.io, Inc (Burlingame, CA)
- …floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle. ... processor architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own… more
- quadric.io, Inc (Burlingame, CA)
- …Electrical Engineering or Computer Science + 7+ years of experience in FPGA design and implementation + Experience with FPGA and/or HAPS top-level systems Vivado or ... equivalent toolchain + Experience with implementing flows to map CPU/GPU RTL on FPGA based platforms for emulation purposes Responsibilities + Develop flows to run… more
- Siemens Digital Industries Software (San Francisco, CA)
- …**Req ID:** 415733 _Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to ... to deliver better products in the increasingly complex world of chip, board, and system design ._ **The Story** This is a unique opportunity to be part of a strategic… more