- US Tech Solutions (San Francisco, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... **Job Description:** + The project relates to the design and verification of a custom...in analog and real number modeling preferred **Skills:** + UVM (Universal Verification Methodology) + FPGA tools… more
- Google (Mountain View, CA)
- …3 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... an emphasis on computer architecture. + Experience in low-power design verification . Be part of a diverse...and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
- Google (Mountain View, CA)
- …in low-power design verification . + Experience with Universal Verification Methodology ( UVM ), SystemVerilog , or other scripting languages such ... verification methodologies and languages such as Universal Verification Methodology ( UVM ) and SystemVerilog ....and ensure documentation is easy to use. + Perform design verification for future CPU developments. +… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... Description:** **Key Responsibilities:** + .Assist the design verification leads to develop software for...basic data structures and algorithms + .Hands-on experience in SystemVerilog / UVM + .Knowledge of UVM … more
- Siemens Digital Industries Software (Fremont, CA)
- …of emulation systems (Veloce/Zebu/Palladium) highly desirable. + Experience in Verilog/VHDL, Verilog, SystemVerilog , UVM for system level verification + ... **Req ID:** 412822 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to… more