- Meta (Sunnyvale, CA)
- … DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and… more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ... implementation and verification of advanced DFT /DFD (Design for Test/Design for Debug) techniques for low...Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.… more
- Broadcom (San Jose, CA)
- …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... Account, please Sign-In before you apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead… more
- Cisco (San Jose, CA)
- …Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow… more
- Qualcomm (Santa Clara, CA)
- …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 5+ years of practical experience with test or DFT … more
- Broadcom (San Jose, CA)
- …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
- Cisco (San Jose, CA)
- …Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...Work closely with chip architecture, design verification, physical design, DFT , and power teams to achieve tapeout success on… more
- Meta (Sunnyvale, CA)
- …entire Silicon Lifecycle, to build and scale silicon for data center applications.As an ASIC Engineer in the Infra Silicon Characterization team, you will be ... ASIC solutions for Meta's data center applications. **Required Skills:** ASIC Engineer - Infra Silicon Characterization Responsibilities: 1. Work across… more
- SpaceX (Irvine, CA)
- SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where ... the ultimate goal of enabling human life on Mars. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer ...+ Work with systems and architecture, SOC integration, verification, DFT , mixed signal, IP owners, synthesis, and place/route teams… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
- Qualcomm (San Diego, CA)
- …largest fabless semiconductor company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and a focus on low ... power, high performance ASIC designs, and, ability to execute critical power analysis...design, verification, synthesis, timing/STA, UPF, CLP, LEC formal verification, DFT , physical design.) + Hands-on experience in writing scripts… more
- Palo Alto Networks (Santa Clara, CA)
- …is to create an environment where we all win with precision. **Your Career** As an ASIC Integration and CAD Engineer , you will ensure that the ASICs in our ... resets, and synchronization. You will collaborate closely with the ASIC vendor and the PANW ASIC design...levels, ensuring robust solutions for clocks, resets, feedthroughs, and DFT + Integrate RAMs, CAMs, custom IPs, and IO… more
- Cisco (San Jose, CA)
- …industry. Who You'll Work With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT , physical design, and post-silicon ... a system company, so you can also use the ASIC to work with the System and Software teams...What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. *… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... BS (or equivalent experience) in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT ,… more
- Cisco (San Jose, CA)
- …on performing project tasks and problem solving. * Collaborate with the verification, PD, DFT , Package and SW teams to develop next generation AI Switching ASIC ... * Bachelor's degree in Electrical or Computer engineering and 15+ years of ASIC Design experience. * Experience with Verilog and System Verilog programming. *… more
- Cisco (San Jose, CA)
- …you directly if a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within Cisco, including marketing, system ... of award-winning communications and network processing silicon/ASICs, Cisco's Core ASIC Group will soon begin development of multiple next-generation designs.… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...implementing Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more