- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer , Physical Design Responsibilities: Develop and own ... Summary: Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer , EDA Infrastructure Responsibilities: Front End implementation flow development ... and support Physical Design implementation flow development and support...tools development and automation to help improve productivity across ASIC design cycles including but not limited… more
- Apple (San Diego, CA)
- …to join us in delivering the next groundbreaking Apple products! Description As a Cellular ASIC Design Engineer , you'll develop and optimize design and ... tools to improve design productivity and reduce turnaround time PHYSICAL DESIGN & IMPLEMENTATION: * Identify utilization bottlenecks in physical … more
- Broadcom (San Jose, CA)
- …engineer capable of leading external and internal cross-functional teams in areas such as physical design , STA, DFT, and packaging? Have you taped out so many ... ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in...teams to prepare and execute risk mitigation actions Execute physical design flows to check that incoming… more
- Broadcom (San Jose, CA)
- …technologies in the industry encompassing 3D and 2.5D interconnects. We are seeking a design engineer with physical layout skills to develop our next ... This is an exciting opportunity to develop new ideas, design the next generation of leading edge ASIC...on the most advanced technologies in the industry. Responsibilities: Design implementation and physical layout implementation of… more
- Google (Sunnyvale, CA)
- SoC Physical Design Engineer corporate_fare Google place Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team ... for complex SoC. Experience with multiple-cycles of SoC in ASIC design . Experience with scripting languages such...AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer , you will… more
- Apple (San Diego, CA)
- …flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to ... BS and a minimum of 10 years relevant industry experience. Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist.… more
- Broadcom (San Jose, CA)
- …and dynamic environment. Hands on experience with timing analysis and place and route tools for ASIC / SoC Design is a must. Should have worked on tape out of at ... before you apply. Job Description: Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure -… more
- Broadcom (San Jose, CA)
- …academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...working on initial floor plan. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation… more
- Northrop Grumman (Acton, CA)
- …quickly and continuously drive innovation. The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In this ... Grumman's Defense Systems is currently seeking a Digital FPGA Engineer Level 3 with the desire to learn new...may be available. Roles and Responsibilities: Responsible for research, design , and development for complex high speed digital designs.… more
- SanDisk (Milpitas, CA)
- …group ESSENTIAL DUTIES AND RESPONSIBILITIES: In charge of form factor PCB design , bringup, validation to meet the product requirement. Work content includes: Lead ... end-to-end SSD hardware design from schematic and layout through bring-up, validation, and...signal routing, power delivery, and mechanical integration. Collaborate with ASIC , firmware, mechanical, and system teams to meet performance,… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. Minimum of 5 years in Sales Pursuit Management. ... with foundries, EDA companies, and IP providers. Background in ASIC Design or Semiconductor Technology R&D is...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- NVIDIA (Santa Clara, CA)
- …Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working ... our CPU team, you'll be a liaison between Logic design and Physical design teams...expertise is preferred as is a deep understanding of ASIC design flow including RTL design… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...+ Experience with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to… more
- Amazon (Cupertino, CA)
- …we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze ... Basic Qualifications - BS + 8yrs or MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
