- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- SpaceX (Irvine, CA)
- …or computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $170,000.00 - $230,000.00/per year Your… more
- SpaceX (Irvine, CA)
- SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where ... the ultimate goal of enabling human life on Mars. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer ...as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA /Timing Engineer /Level I: $120,000.00 - $145,000.00/per year… more
- Qualcomm (San Diego, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Qualcomm (San Diego, CA)
- … ASIC /SoC design flows (micro-architecture, RTL design, verification, synthesis, timing/ STA , UPF, CLP, LEC formal verification, DFT, physical design.) + Hands-on ... company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and...skills, and a focus on low power, high performance ASIC designs, and, ability to execute critical power analysis… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Amazon (San Diego, CA)
- …Engineering or related field, or equivalent experience. * 7+ years of experience in ASIC implementation, ie, synthesis, STA and working with P&R for deep ... flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design...Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Broadcom (Irvine, CA)
- …and 8+ years of industry experience in flow development , synthesis constraints development / STA is a must, or MSEE and 6+ years of industry experience. A strong ... be responsible for working on automating design flows, supporting synthesis deliverables & STA . Apart from this, the candidate is also expected to handle minimal… more
- Amazon (Hawthorne, CA)
- …front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining ... test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans - Write high quality documents to guide a scalable team Basic Qualifications - Bachelor's degree in Electrical Engineering, Communications Engineering or… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing. + Good knowledge of extraction,… more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, ... RTL 2 Gate and Gate 2 Gate. + Run STA on final netlist and support PD timing/congestion closure...Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Broadcom (Irvine, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...range of products that keep the globe connected. Our ASIC products division is looking for senior, physical design… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...including standard cells/memory/IO/IP modeling and its usage in the ASIC flow. * Background in debugging and analyzing timing… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the ... of the usage modes and debug tools. The Palladium ASIC team has a wide range of expertise from...Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint… more