- Qualcomm (Folsom, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (San Diego, CA)
- …and implement multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer, you will work with microarchitecture and RTL ... power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits ** Physical Requirements** + Frequently transports between… more
- Qualcomm (Santa Clara, CA)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and...nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical … more
- Qualcomm (San Diego, CA)
- … (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... coverage collection, gate level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical and MAC layer… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Experience with simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power implications. **Preferred… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- Qualcomm (San Diego, CA)
- …and develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading ... the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330...basic soc architecture. Be able to work with Front-end design team to address timing , congestion and ... Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr..../ RDL routing, power grid generation, full chip STA timing , DFT strategy planning, and final physical … more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... + On-chip tightly coupled SRAM & L3 cache controller architecture/ design + Experience with x86 or ARM CPU...architecture/ design + Experience with x86 or ARM CPU /bus architectures + Ordering of memory transactions and methods… more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... a smarter, connected future for all. QCT Memory Controller Design Team is looking for ASIC Design ...interfaces to the rest of the system such as CPU , DSP, Multimedia Processors and the engineer is expected… more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... FPGA design flow (eg synthesis, timing closure, formality...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- Broadcom (San Jose, CA)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. + In-depth CPU /DSP architecture/algorithm working ... System-On-Chip ASICs. Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for ... work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are...tools including Genus Synthesis, Innovus P&R and Tempus Static Timing Analysis flows is expected. The Intern needs to… more
- Qualcomm (San Diego, CA)
- …embedded memory design flow: architecture, circuit design , physical implementation, compiler automation, characterization, timing and model generation + ... products. This is a highly visible role where your design will highly influence various parts of CPU... design will highly influence various parts of CPU /GPU/Modem/NSP/Camera designs. Positions will be located in San Diego,… more
- Cisco (San Jose, CA)
- … design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * Triage, debug, ... participate in reviews * Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable. * Design experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …experience working on IC physical designs tools.Hands on experience using the above physical design tools for design closure and knowledge of physical ... critical step for various optimization objectives of a chip design , including timing (how fast a chip...variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done… more
- General Motors (CA)
- …next-generation vehicles. We are seeking an experienced platform software engineer to design and develop platform software for ADAS embedded platform. Your expertise ... stack. **The Role:** As Staff Software Engineer, Platform, you will: + Design and code development of safety critical platform applications using C, C++14… more