• Chip Power Architecture

    NVIDIA (Santa Clara, CA)
    We are now looking for a Chip Power Architecture Lead ! NVIDIA is seeking an exceptional Chip Power Architecture Lead to help us build ... Engineering, Electrical Engineering (or equivalent experience) + 10+ years of Chip / Power Architecture experience + Excellent leadership capabilities to… more
    NVIDIA (11/26/24)
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  • Senior Staff Chip Package Signal Integrity…

    Google (Sunnyvale, CA)
    …Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture . + Experience working cross functionally with chip top design, ... a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the… more
    Google (01/09/25)
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  • DRAM Pathfinding and Architecture

    Micron Technology, Inc. (San Jose, CA)
    …the world to learn, communicate and advance faster than ever. As DRAM Pathfinding and Architecture Lead you will lead the DRAM pathfinding and ... use cases and modelling strategies for target workloads to lead architecture tradeoff decisions. This may include...their corresponding memory and storage access patterns and emulating architecture elements and improvements in power and… more
    Micron Technology, Inc. (12/25/24)
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  • Signal and Power Integrity Engineer

    Google (Sunnyvale, CA)
    …performance, efficiency, and integration. In this role, you will lead chip and package design, ensuring optimal Signal Integrity/ Power Integrity (SI/PI) ... Design, software, and vendors, you will drive signal and power design implementations on chip and advanced...packages. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep… more
    Google (01/09/25)
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  • Infrastructure Tools and Methodology Lead

    Google (Sunnyvale, CA)
    …number of different application areas. Leveraging your technical and leadership expertise, you lead chip design process improvement projects in multiple areas of ... or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) . + Lead chip methodology engineers to provide support for chip more
    Google (01/17/25)
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  • Sr. Physical Design Engineer

    Belcan (Palo Alto, CA)
    …place and route, and close design to meeting performance, power and area. Lead and Perform all aspects of full chip SoC integration activities: die size ... planning, clock tree implementation, routing, STA timing signoff, and chip -finishing. Good knowledge of basic soc architecture .... level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing,… more
    Belcan (01/15/25)
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  • Physical Design Lead , Static Timing…

    Google (Sunnyvale, CA)
    …practical experience. + 10 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static ... and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full- chip static timing topics, including clocking, timing exceptions, time budgeting,… more
    Google (12/21/24)
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  • Senior GPU Power Architect

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior GPU Power Architect! The NVIDIA GPU Architecture group is looking for world class architects and software developers to join and ... lead our various architecture efforts. A key...new features. What you'll be doing: + Work with chip architects to understand architecture concept and… more
    NVIDIA (12/03/24)
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  • Senior Power and Thermal Engineer

    NVIDIA (Santa Clara, CA)
    …role. We need a passionate, hard-working and creative individual to lead the power features all the way from architecture to delivering the features on the ... datacenters to low- power client devices. + Lead the team for power feature requirements and schedule from architecture to silicon phase of projects,… more
    NVIDIA (01/16/25)
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  • Senior System Power Architect

    Ford Motor Company (Sacramento, CA)
    …our team. In this role, you will be responsible for designing and optimizing power architecture for our automotive systems, ensuring they meet the stringent ... products. **In this position ** + Design and develop power architecture specifically for automotive systems, ensuring... reduction and energy efficiency in automotive applications. + Lead the evaluation and selection of automotive power more
    Ford Motor Company (11/19/24)
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  • Senior Hardware Engineer

    Motion Recruitment Partners (Palo Alto, CA)
    …place and route, and close design to meeting performance, power and area. + Lead and Perform all aspects of full chip SoC integration activities: die size ... floorplanning, clock tree implementation, routing, STA timing signoff, and chip -finishing. + Good knowledge of basic soc architecture... level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing,… more
    Motion Recruitment Partners (01/17/25)
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  • Power Architect, Platforms Engineering

    Google (Sunnyvale, CA)
    …load application. Your objective will be to design, analyze, optimize and implement board, chip level power topologies and control for large scale point of load ... processors. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep...new uses of multiple existing technologies. + Partner with power industry leaders to lead evaluation and… more
    Google (01/08/25)
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  • Senior Software Engineer - Hardware Abstraction…

    Amazon (Cupertino, CA)
    …the backend software that manages these servers. We're looking for someone to lead our system-on- chip hardware abstraction layer (SoC HAL) software team. You'll ... hands-on, in-the-trenches software engineering leadership position. As the team lead for SoC HAL SW, you will: - ...- Enjoy working with hardware-based systems, and diving into chip and system architecture - Love solving… more
    Amazon (12/15/24)
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  • Testchip Backend Lead

    Google (Mountain View, CA)
    …. + Develop bump, micro-bump, chiplets plan to support new test- chip development. + Work with packaging and architecture teams ... tapeout of SoC in physical design + Experience with full- chip IO, clocking, and block placement Preferred qualifications: +...SERDES IP integration such as PCIe, D2D UCIe, low power IP into SoC. + Excellent statistics, data analysis,… more
    Google (01/11/25)
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  • Senior System Power Management Engineer

    NVIDIA (Santa Clara, CA)
    …methodologies. + Strong EE fundamentals, knowledgeable in digital design, computer architecture , power analysis, timing analysis, fault analysis, sampling, ... goals, find opportunities, and work across teams to develop and propose new power management features. Your contributions will directly impact the next generation of… more
    NVIDIA (01/17/25)
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  • SiliconOne Electrical Validation Lead

    Cisco (San Jose, CA)
    …SDK, test execution and results analysis. You will gain detailed knowledge of chip architecture , functionality and operation modes allowing you to debug and ... the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon… more
    Cisco (10/24/24)
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  • Lead Analog Mixed-Signal Layout Design…

    The Boeing Company (Huntington Beach, CA)
    …for professional growth. Find your future with us. Boeing is seeking a ** Lead ** **Analog Mixed-Signal Layout Design Engineer** to join our team in **Huntington ... for aerospace systems. SSED develops digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other… more
    The Boeing Company (01/13/25)
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  • Lead Analog Mixed Signal Design Engineer

    The Boeing Company (Huntington Beach, CA)
    …for aerospace systems. SSED develops digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other ... fabrication services but executes the whole design flow in-house ( architecture definition, circuit design, RTL, synthesis, physical layout, verification, packaging… more
    The Boeing Company (01/09/25)
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  • ASIC STA Engineer

    Cisco (San Jose, CA)
    …work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints ... with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. * Familiarity with various on- chip variation including AOCV,… more
    Cisco (11/08/24)
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  • Silicon Packaging Design Engineer

    Meta (Sunnyvale, CA)
    …Responsibilities: 1. Perform package design for advanced custom silicon comprising single- chip /multi- chip and 3D or wafer packaging. This includes: design ... feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements 2. Participate in… more
    Meta (01/17/25)
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