- NVIDIA (Santa Clara, CA)
- …This role offers a great opportunity to be at the forefront of compiler verification , ensuring our brand-new technology maintains its premier standard. You ... like GDB, LLDB; ELF and Dwarf Standards. + Previous experience in compiler development, verification /testing, or performance analysis; plus unit-test development… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly ... skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this… more
- Google (Sunnyvale, CA)
- …and verification for SoCs. + Experience in silicon bring-up, debug , or validation of DFT features. + Experience with industry-standard test methodologies ... SoC DFT Engineer , Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA,...10 years of experience in DFT architecture, implementation, and verification for SoCs. + Experience with various fault models… more
- Micron Technology, Inc. (San Jose, CA)
- …design and RTL; 3. Analog circuits; 4. Mixed-mode design and validation; 5. Design/ Verification CAD tools, including NCSim. 6. Design Compiler , Formality, or ... Responsible for contributing to the design team's success by applying functional verification tools and techniques to 3D-NAND non-volatile memory designs. Work daily… more
- Micron Technology, Inc. (Folsom, CA)
- …verbal and written communication skills. + Strong problem-solving skills in physical verification and debug . + Experience supporting multiple tape-outs and ... California is seeking a highly experienced **Custom Layout and High-Speed I/O Design Engineer ** to help shape the future of memory solutions for AI and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... Logical Equivalency Checking + Low Power Design Implementation, SDC Verification + Place and Route + Parasitic Extraction, Timing...4+ years of experience in Synthesis (Genus or Design Compiler ), DFT and Logic Equivalency tools Or Cadence or… more