- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Cisco (San Jose, CA)
- …or MS Degree in Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow ( STA ) and methodology. * Hands-on experience ... timing and routing congestion issues, influencing key design and physical implementation decisions early in...constraints generation and validation, clock domain crossing checks, and timing closure. * Expertise in STA tools… more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA / Timing Engineer/Level I: $120,000.00 - $145,000.00/per year ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...Physical Design STA / Timing Engineer/Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or ... Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should...considered for this position. Candidate should extremely proficient in design implementation activities both at block and… more
- Qualcomm (San Diego, CA)
- …static timing analysis ( STA ) for complex digital designs. - Collaborate with design , verification and PD teams to ensure timing closure and design ... STA scripts and methodologies. - Analyze and resolve timing issues, working closely with cross-functional teams. - Run...power checks and Logic equivalency checks. - Participate in design reviews and provide feedback on timing … more
- Broadcom (San Jose, CA)
- …error messages from the timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC ... analysis, and other timing checks - Ability to understand and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF… more
- Capgemini (San Francisco, CA)
- …Physical Verification at both block and chip level *Understanding constraints and fixing design / timing techniques *Block level implementation from netlist to ... level and/or blocks, with experience across the complete ASIC/SOC design flow including routing, static timing closure,...PnR, CTS, block integration and ECO generation. *Expertise in timing closure ( STA ) of high frequency blocks… more
- Capgemini (San Francisco, CA)
- …Verification at both block and chip level + Understanding constraints and fixing design / timing techniques + Block level implementation from netlist to ... **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)**...CTS, block integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks… more
- Amazon (San Diego, CA)
- …to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC ... equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with...Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical design .… more
- Capgemini (Santa Clara, CA)
- …for Lint/CDC issues, checking synthesizability and timing quality of the design , checking low power implementation , supporting verification team with debug ... specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA...and support physical design teams on … more
- NVIDIA (Santa Clara, CA)
- …logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation and ... understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. + Experience in...and/or flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- Broadcom (San Jose, CA)
- …Expertise in micro-architecture design and PPA trade-offs. + Experience in synthesis, STA , and timing closure using tools like Synopsys DC or Cadence Genus. ... a Staff Digital Front-End Designer, you will own the design and implementation of complex digital IP...You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing … more
- Qualcomm (San Diego, CA)
- …Aware Conformal Logic Equilalency Check: both RTL 2 Gate and Gate 2 Gate. + Run STA on final netlist and support PD timing /congestion closure + Work with RTL ... As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and...RTL designers on managing complex power intent + Manage timing constraints + Trouble shoot upf issues in synthesis… more
- Qualcomm (San Diego, CA)
- …SoC implementation team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium ... chips. This is a great opportunity to join Snapdragon implementation team responsible for SoCs in sub-3nm nodes in...power. + Generate, review and validate clock domain crossing, design constraints to achieve timing closure of… more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- Qualcomm (San Diego, CA)
- …tradeoffs Programming and scripting skills Strong collaboration and communication skills STA timing Power analysis **Minimum Qualifications:** * Bachelor's ... to work on QUALCOMMs Adreno Graphics cores in the area of Graphics implementation , Advanced Process Technology and methodology. The Design Technology Engineer… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation +...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Cisco (San Jose, CA)
- …sign off checklist and reviews for chip tape out, including test coverage, STA . * Prior experience with pre-silicon DFT implementation and verification flows, ... in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a...including, System Verilog Logic Equivalency checking and validating the Test- timing of the design * Prior experience… more
- Qualcomm (Santa Clara, CA)
- …of practical experience. + Proficiency in synthesis, place and route, and signoff timing /power analysis. + Expertise in block-level implementation as well as ... and Integration Engineer, you will work with microarchitecture, RTL design and physical design teams to ...a team environment. + In-depth understanding of extraction, static timing analysis ( STA ), and electromigration and IR… more