- Qualcomm (San Diego, CA)
- … ASIC engineers with excellent analytical and technical skills, and a focus on low power , high performance ASIC designs, and, ability to execute critical ... low power designs. + Strong knowledge in the entire low power , high performance ASIC /SoC design flows (micro-architecture, RTL design, verification,… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and ... **Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure...abstraction: C-model, RTL, Gate, Layout. 6. Optimize design for low - power with the understanding of system level… more
- The Boeing Company (El Segundo, CA)
- …Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for an ** ASIC and/or FPGA Design and Verification Engineer ** **(Experienced, Lead or ... Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- The Boeing Company (Huntington Beach, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. And we're applying the latest...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- SpaceX (Irvine, CA)
- … power intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...flow, top-down and bottom-up design methodologies + Knowledge of low - power methodologies and leakage/dynamic power … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to ... can create as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI/PI Responsibilities: 1. Drive chip-package-system co-design… more
- Capgemini (San Francisco, CA)
- **Job description:** Experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the ... Design Validation teams to support SI/PI failure analysis *Package/Board power delivery network AC DC simulation for low...**Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Physical Design Engineer - ASIC Package Engineer … more
- MetaOption, LLC (Milpitas, CA)
- Sr. Front-End ASIC Design Engineer Candidate needs SoC/ ASIC experience working hands on currently, with non-off the shelf designs. - Compute (ie, CPUs), ... are useful experience. Description We are seeking a Front-End SoC/ ASIC Design Engineer for our SoC business...RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low - power design and verification; high-speed peripheral interfaces… more
- Amazon (Cupertino, CA)
- Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...ownership and deliveries * 3+ years of experience with power analysis and optimization * Experience working with SOC… more
- Capgemini (San Francisco, CA)
- **Job description:** Capgemini Engineering is looking for an experience ASIC Package Engineer to join our semiconductor domain. The engineer will be working ... and improve design flow. + Work closely with Architecture, ASIC , Mixed Signal, Package, and PCB Design teams to...Validation teams to support SI/PI failure analysis. + Package/Board power delivery network AC DC simulation for low… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 19. Experience with low power implementation, power gating,… more
- Meta (Sunnyvale, CA)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 20. Experience with development of… more
- Kelly Services (Milpitas, CA)
- **Front-End ASIC Design Engineer Milpitas, CA** **$150,000 to $200,000 Annually** **Job Description** A new, innovative enterprise that designs, develops and ... development and sales activities. We are seeking a Front-End SoC/ ASIC Design Engineer for our SoC business...or GPU, or DSP + SoC Memory hierarchy; NoC/Fabric; low - power design and verification + High-speed peripheral… more
- Meta (Sunnyvale, CA)
- …Memories. 23. Knowledge of STA signoff and understanding of AOCV, POCV 24. Experience with low power techniques for reducing power . 25. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Qualcomm (San Diego, CA)
- …designers at various levels to help with designing high-speed, high-performance and low - power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) ... applications. QCT mixed-signal design team consists of architects and ASIC designers, protocol experts, signal processing engineers, and algorithm designers… more
- Amazon (Sunnyvale, CA)
- …implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design… more
- Amazon (Cupertino, CA)
- …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
- Cisco (San Jose, CA)
- …* Experience in interactive and waveform debug skills. * Experience with low - power design and clock domain crossings. Preferred Qualifications * Experience ... developed in the industry. Your Impact You will collaborate with architects, ASIC front-end and Design Verification teams to understand chip architecture, implement… more
- NVIDIA (Santa Clara, CA)
- …crowd: + Pipeline processor or deep learning accelerator design/architecture experience + Low power or physical (synthesis/VLSI) design experience + Scripting ... We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is...and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements. + Execute and deliver… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... What you'll be doing: + You will drive physical design of high-frequency and low - power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level,… more