- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly ... to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI,… more
- Meta (Sunnyvale, CA)
- …technology. To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Develop power vectors ... for estimation and optimization. 2. Low - power design of ASIC modules. 3. Run industry standard EDA power simulation tools on customized ASIC designs.… more
- Google (Sunnyvale, CA)
- Senior ASIC Power Engineer , ML...Level) design using Verilog or SystemVerilog. + Experience with low - power design or power reduction ... + 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with RTL (Register...techniques. + Define best practices and methodologies to achieve low - power RTL designs. + Collaborate with cross-functional… more
- SpaceX (Irvine, CA)
- …AHB, etc.) + Experience with embedded processors + Experience with high speed and low power design techniques + Scripting skills (Python, TCL etc.) + Experience ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...to solve complex problems including clock domain crossings and power optimization + ASIC /SoC system integration experience… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning 19. Experience with low power implementation, power gating,… more
- Teledyne (Goleta, CA)
- …analysis. + DFT/ATPG insertion (scan chains, BIST for ASIC testability). + Clock/ Power optimization for low - power ASICs. + Perform Back-End Physical ... on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer : Oversees definition, design,...windowing). + Finite State Machine and datapath design for ASIC modes. + Clock domain crossing and power… more
- Meta (Sacramento, CA)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 22. Experience with development of… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...for testability (eg, IEEE 1500, 1687) and experience with low - power DFT techniques using Siemens Tessent +… more
- Amazon (Cupertino, CA)
- …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
- Google (San Diego, CA)
- Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA **Mid** Experience driving progress, solving ... years of industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... What you'll be doing: + You will drive physical design of high-frequency and low - power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level,… more
- Amazon (San Diego, CA)
- …- Experience with products that have gone to volume production - Experience in low power design techniques Preferred Qualifications - Master's degree or Ph.D. ... Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing… more
- Amazon (Sunnyvale, CA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities -Define architecture specifications based on requirements… more
- Broadcom (Irvine, CA)
- …PPA tradeoffs involved amongst various library components, and architectures + Knowledgeable in low power design and power management + Hands-on experience ... industry, including AI. Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in areas such as AI, HPC,… more
- NVIDIA (Santa Clara, CA)
- …of concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC design principles, including ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA...Our team is responsible for analyzing fullchip and unit-level power data, and driving ASIC teams to… more
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + Build roadmaps of memory system-level features to address low power , low noise, perf/watt efficient, and stable/reliable product ... or high-perf systems. + Strong fundamentals in EE, digital/analog design, signal integrity, low power design, memory power management techniques, timing… more
- Meta (Menlo Park, CA)
- …our cutting-edge data centers affecting billions of users. Meta is seeking an Electrical Engineer to join our Power Systems team. Our team is responsible for ... contributed to the Open Compute Project. **Required Skills:** Electrical Engineer , Power Responsibilities: 1. Define system end...current, as well as high voltage and high current power subsystems of CPU, GPU, SoC, ASIC … more
- NVIDIA (Santa Clara, CA)
- …a member of this team, you are responsible for developing and validating system level low power features with a deep understanding of products needs that will ... you will be doing: + Bring up system level low power features to address existing and...lab tools (oscilloscopes, multimeters, logic analyzers). + Experience with ASIC power saving features and methods +… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **System Signal/ Power Integrity Engineer ** _Responsibilities_ + Support high data rate ... + Power Integrity Concepts: PDN impedance analysis and design, ultra- low impedance measurements, understanding of SMT capacitor performance metrics, use of CPA… more