- Silvus Technologies (Irvine, CA)
- …coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. ... Experience using MATLAB. + Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. +… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Senior Engineering Director_ in ... coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers.… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... Make the choice to join us today. With the System- ASIC team, you will contribute to designing multiple products...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- RTX Corporation (El Segundo, CA)
- …of a rapidly evolving global market. This position is for a motivated Senior Electrical or Computer engineering candidate to be involved in the design, ... Technologies team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL,... / FPGA digital architecture and design using RTL, timing closure, verification, and system integration + Recommend new… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... to see: + MS/Phd in Electrical Engineering or Computer Engineer or related degree (or equivalent experience). + 5+...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to have real ... to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/ timing clean design. + Support post-silicon validation activities. + Work with… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic ... checks, etc. + Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate with architects, verification engineers, formal… more
- Google (San Diego, CA)
- Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA **Mid** Experience driving progress, ... like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. **Preferred qualifications:** + Master's degree or PhD in Electrical… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Strong familiarity and experience with all stages of ASIC design flow including front end design and verification,...flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding interpersonal… more
- SpaceX (Irvine, CA)
- …to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...that in top level and deliver the fully verified, synthesis/ timing clean design + Work closely with verification team… more
- Amazon (Sunnyvale, CA)
- …Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and ... in design methodologies and EDA tools - Experience working with Synthesis, timing closure, and design constraints Preferred Qualifications - Experience with ARM and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... architects, platform, and software teams. + Partner with design, verification, synthesis, timing , and backend teams to ensure cohesive integration. + Create and… more
- NVIDIA (Santa Clara, CA)
- …on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on ... Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the unit....expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT,… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
