- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- Meta (Sunnyvale, CA)
- …test cases using industry-standard verification languages and methodologies (eg 4. SystemVerilog , UVM ). 5. Perform simulation and debugging of ASIC designs ... 2. Collaborate with design engineers to understand design intent and identify potential verification challenges....languages (eg Verilog) and verification languages (eg SystemVerilog ) with in UVM (Universal Verification… more
- Capgemini (Santa Clara, CA)
- …and Implement Solutions** Design and deploy **end-to-end SoC verification environments** leveraging UVM , UPF, and advanced methodologies. **Engineer ... accelerate delivery. **Your Profile** + **15 years** in SoC design / verification with expertise in UVM ,...UVM , UPF, and protocol VIPs. + Proficiency in ** SystemVerilog ** , **VHDL** , and scripting languages (Python, TCL).… more
- Amazon (Sunnyvale, CA)
- … verification , preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development ... . Participate in the validation of ASIC implementations in Verilog/ SystemVerilog . Run formal verification of complex...and communication systems team and participate in system level verification using test benches constructed using UVM ,… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …or related field 5+ years experience with SystemVerilog , VHDL, Verilog Verification skills such as UVM testbench architecture, development and debug Strong ... R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design... verification flows and AI/ML applications to secure design wins - Champion the customer needs and work… more
- Palo Alto Networks (Santa Clara, CA)
- …relationships, and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ... MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking...products from concept to mass production + Expertise in SystemVerilog and UVM + Technical strength in… more
- Microsoft Corporation (Santa Clara, CA)
- …across geographic regions towards project completion. + Develop comprehensive pre-silicon verification test plans based on design specifications and performance ... requirements. + Create and maintain UVM / SystemVerilog -based testbenches for block-level, cluster-level, fullchip and...resolve design issues. + Understanding of digital design , computer architecture (ARM, RISC-V, MIPS), and verification… more
- Teledyne (Milpitas, CA)
- …+ Integrate PCIe IP cores, DMA engines, and custom protocol decoders. + ** Verification & Debug** + Build SystemVerilog / UVM testbenches for block ... teams to deliver industry-leading solutions. **Key Responsibilities** + **RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/ SystemVerilog )… more
- NVIDIA (Santa Clara, CA)
- …with assertion-based verification , Semiformal Verification (SFV), Unified Verification Methodology ( UVM ), SystemVerilog checkers and scoreboards. + ... to the design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your unit + Support post-silicon… more
- NVIDIA (Santa Clara, CA)
- …server platforms + Working Knowledge of CPU - GPU coherency + Experience with UVM verification environments and scripting with Perl, Python and C/C++ is ... essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Zebu emulation experience with SOC/CPU… more
- NVIDIA (Santa Clara, CA)
- …experience. + Individual should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog . + Experience with UVM verification environments and scripting ... C/C++ is essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Candidates will be working on-site… more