- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- SpaceX (Irvine, CA)
- Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer ...& validation + Develop block and full chip level timing constraints for test modes + ... goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...timing closure in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation… more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/ Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design ... internet to millions of users worldwide. We design, build, test , and operate all parts of the system -...STA/ Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …or related experience * Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working ... from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Cisco (San Jose, CA)
- …development - Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation ... in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend...What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE, in-system test… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... next-generation quantum instruments. + Set up CI/CD pipelines and test server racks for devices-under- test (DUTs). +...CI/CD pipelines and test server racks for devices-under- test (DUTs). + Create and maintain automation scripts in… more
- Teledyne (Goleta, CA)
- …excitement of being on a team that wins. **Job Description** **Analog Design Engineer :** Designer in charge of architecting analog circuits for infrared focal plane ... As part of the design phase determines architecture and timing from the analog input to driving all digital...and trades for peer and customer reviews. Works with test and systems engineers through characterization of final products.… more
- Northrop Grumman (Manhattan Beach, CA)
- …Strategic Space Systems) in Manhattan Beach, CA is seeking a talented Principal Engineer Digital/Sr. Principal Engineer Digital. This person will be required to ... (but not limited to) develop, test , and integrate complex digital hardware and support ...requisition can be filled at a level 3 Principal Engineer Digital or a level 4 Sr. Principal … more
- Belcan (Palo Alto, CA)
- …expected operation sequences, and their corresponding results, including Register maps, Timing diagrams, Command sequences Develop test vectors based on ... Senior Hardware Engineer Job Number: 353813 Category: Electrical / Electronics...and invalid input scenarios, edge cases for register settings, timing and sequence requirements; enhance the test … more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- Control System Engineer Job ID 6186 Location SLAC - Menlo Park, CA Full-Time Regular **SLAC Job Postings** **Position overview:** Do you enjoy collaborating with a ... (LCLS) Directorate at SLAC is seeking a Control System Engineer to join the Engineering and Design controls team....of tools and applications for experiment laser control and timing control systems. LCLS is the world?s first hard… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- Actalent (El Segundo, CA)
- Job Title: FPGA Engineer Job Description We are seeking a skilled Digital ASIC/FPGA Design Engineer to support our Satellite Capabilities organization and ... detailed design documentation. + Perform HDL coding, logical equivalency checking, static timing analysis, CDC, and linting. + Integrate third-party IP. + Create… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- The Boeing Company (Huntington Beach, CA)
- …is currently seeking a **Digital Integrated Circuit Physical Design Engineer (Associate, Mid-Level or Senior)** with experience developing complex, high-performance ... design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test ) in house. SSED has numerous microelectronics projects, funded both… more
- Qualcomm (Santa Clara, CA)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools ... responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning,… more
- BAE Systems (San Diego, CA)
- …assisting in design architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing, product support ... an open position for a Senior FPGA Digital Design Engineer ! See what you re missing. Our employees work...of internal logic analyzer (ILA/chipscope/signaltap) + Familiarity with static timing analysis tools and timing closure +… more
- Sacramento County (Sacramento, CA)
- Associate Transportation Engineer Print (https://www.governmentjobs.com/careers/sacramento/jobs/newprint/4510739) Apply Associate Transportation Engineer ... are at 5:00 pm on: 12/27/2024, 1/10/2025, 2/7/2025 (Final) Associate Transportation Engineer is the first level in the transportation engineering series requiring… more
- Meta (Sunnyvale, CA)
- …and verification. 3. Define timing constraints, run synthesis and static timing analysis. 4. Support the test program development, chip validation and ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...including UPF flow. 19. Experience with design synthesis and timing optimization. 20. Master's degree in Computer Science, Computer… more
- Qualcomm (San Diego, CA)
- …federal, local, and foreign governments. In this role as a Hardware Engineer , you will support government-sponsored research, development, integration and test ... for working closely with other engineering disciplines to design, develop, test , automate, and document communication capabilities. Excellent written and verbal… more