- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Sunnyvale, CA)
- …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 14+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …based verification . 9. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Track ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs,...15. Experience in development of UVM based verification environments from scratch. 16. Experience with Design… more
- Meta (San Diego, CA)
- …UVM methodology. 10. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... 9. 3+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and ...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Meta (Sunnyvale, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Northrop Grumman (Mcclellan, CA)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Qualcomm (Santa Clara, CA)
- …PCIe controller, Coherent Interconnects, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage ... is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology... SystemVerilog + 5+ years of experience with verification methodologies such as UVM or OVM… more
- Qualcomm (San Diego, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology...and methodology + 3+ years of experience with digital design concepts and RTL languages such as SystemVerilog… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... growing your skills, and advancing your career. BAE is looking for experienced FPGA Design Verification Engineers who can develop and use verification … more
- Qualcomm (Santa Clara, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... this is where you come in as an ASIC Design Verification Engineer The team is responsible...flow and methodology. Involve in developing automation to improve verification efficiency. **Qualifications:** + DV experience using uvm… more
- Capgemini (San Francisco, CA)
- …Engineer** **Job Location:** **San Francisco CA** **Job Description** We are seeking Senior Design Verification Engineer for our Full Time role with Capgemini ... basic tests, compile, and build hex code for processor tests. + Engage in design verification involving concurrency and simultaneous memory access. + Define and… more
- Amazon (Cupertino, CA)
- …- Expertise in various verification languages and tools such as SystemVerilog , UVM , Verilog, and simulation/emulation platforms - Proven track record of ... Qualifications - 8+ years of hands-on experience in ASIC/VLSI design verification , with a strong understanding of... verification , with a strong understanding of verification methodologies such as UVM , along with… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify...models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM . + Build… more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Cisco (San Jose, CA)
- …experience working in C++, scripting, as well as ASIC design and verification flow. * Defining and building UVM / SystemVerilog testbenches from scratch ... of very complex ASICs. You will have a Design Verification background, in-depth experience in System...Help develop emulation infrastructure using C/C++ that works with UVM based verification environments. * Gate level… more