- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- MetaOption, LLC (Milpitas, CA)
- Physical Design Engineer - Milpitas, CA We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and ... experience. Local candidates are preferred. Key Responsibilities: + Pre-layout STA for feasibility and timing constraint validation + Chip/block-level floorplanning… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
- Broadcom (San Jose, CA)
- …Description:** Broadcom's CSG division is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for developing and ... for test. **Responsibilities** + Own IP DFT architecture, implementation, verification, signoff STA constraints for DFT + Optimize DFT architecture for test cost,… more
- Broadcom (San Jose, CA)
- …and methodologies to achieve desired PPA metrics. + Complete equivalence checks, STA , Timing closure and power optimization. + Implement timing and functional ECOs. ... Desired:** + Primary expertise in place and route and/or timing (constraints, STA ) can be considered for this position. + Proficient in design implementation… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... **Requirements:** + Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. + Extremely proficient in design… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves working ... Timing closure through various methods and strategies; preferable in-depth experience in top-level STA + EM/IR Analysis, + Place and Route + Clock Tree Synthesis;… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis ( STA ).You may get involved in design services projects and/or supporting customers… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …an impact in our world. We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug, and production ramp for advanced memory IP ... presentation, and communication skills. Preferred / Optional Skills + Exposure to STA and RTL flows would be beneficial. + Familiarity with advanced mixed-signal… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …analysis platform development. + Proficiency in logic design, simulation, synthesis, STA and testing + Proficiency in Verilog/SystemVerilog and its simulation ... environment + Good knowledge of IC design for high-speed and low power + At least five years' experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team… more
- Broadcom (San Jose, CA)
- …standard cells placements/clock tree adjustments/routing to achieve design specs ( STA /IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required. - ... MSEE/MSCS 6+ years (BSEE/BSCS 8+ years) - Expertise in Cadence Innovus/Atop physical design tools - Experience on Calibre LVS/DRC - Low power, signal integrity experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required,… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such ... as physical design, STA , DFT, and packaging? Have you taped out so...Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in… more
- Cisco (San Jose, CA)
- …to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more