- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a DV Infrastructure Engineer focusing on the methodology and support of ... solutions tied to internal and vendor-based RTL/Verification CAD tools. + Interact with DV team to diagnose the root cause of complex problems, propose solutions to… more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CAD Engineer focusing on the DV & Emulation methodology and support, you ... will work with RTL, architecture, design, DV , software and silicon verification users. Interfaces with various cross functional teams and external vendors to define,… more
- Cisco (San Jose, CA)
- …* Bachelors of Science Electrical Engineering or Computer Science or related degree * 4+ years of related experience in ASIC or Silicon * 4+ Years of experience with ... System Verilog * 4+ Years of experience with ASIC Verification processes, methodologies, flows and tools * Experience with scripting languages Python or Perl Preferred Qualifications * SEE/CS combined with 3+ years of related experience * Understanding of… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CAD Engineer focusing on the methodology and support of RTL design verification, you ... will work with architecture, design, software and verification leads to develop technology critical to the development of our products. You will be involved from conception to final creation and every step along the way. Roles and Responsibilities + Work with… more
- Capgemini (Sunnyvale, CA)
- **Position- Mixed Signal DV Engineer ** **Location-** **Sunnyvale CA - Onsite role** **Job description:** We are seeking Mixed signal Design Verification ... Engineer who is proficient in system verilog real number...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Cisco (San Jose, CA)
- …Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer /lead to engage in new development of our UCS family. You will have an ... semiconductor markets. * Architect block, cluster and top level DV environment infrastructure * Create DV infrastructure...top level DV environment infrastructure * Create DV infrastructure from scratch for block, cluster and top… more
- Cisco (San Jose, CA)
- …and security. Specific responsibilities include: * Architect block, cluster and top-level DV environment infrastructure. * Develop DV infrastructure from scratch ... cluster and top-level environments. * Maintain and enhance existing DV environments. * Develop test plans and tests for...is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation… more
- Qualcomm (Santa Clara, CA)
- …planning & critical debugs + Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV methodologies (formal, simulation, and emulation ... Python is a plus + 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of major SoC blocks + 2+ years' leadership… more
- Randstad US (Mountain View, CA)
- hardware engineer . + mountain view , california + posted 6 days ago **job details** summary + $93.33 - $107.55 per hour + contract + bachelor degree + category ... mathematical occupations + reference1070996 job details job summary: A Hardware Engineer is needed for an American multinational technology company that develops,… more
- Lightmatter (Mountain View, CA)
- Sr. Staff Design Verification Engineer Lightmatter is a photonic computer company that is redefining what computers and human beings are capable of by building the ... Lightmatter! We are hiring a Sr. Staff Design Verification Engineer to join our team and help orchestrate the...coverage, and overseeing the final sign-off on Design Verification ( DV ). + Develop Real Number Models (RNM) for photonics… more
- Cisco (San Jose, CA)
- …complex ASICs being developed in the industry. What You'll Do As ASIC Verification Engineer in The Core Hardware Business Unit, you will be engaged the following ... tasks: *Implementation of DV infrastructure for block, cluster and top level environments....for block, cluster and top level environments. *Maintaining existing DV environments and enhancing them *Ensuring complete verification coverage… more
- Cisco (San Jose, CA)
- …in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, ... and during ASIC bring up. What You'll Do: * Maintaining existing DV environments and enhancing them * Construct testbench including scoreboard, agents, sequencers,… more
- Qualcomm (Santa Clara, CA)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the concepts of CPU ... for your functional domain. + Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and… more
- Qualcomm (Santa Clara, CA)
- …Standards, creating test sequences, and validating design components + Own end-to-end DV tasks from coding Test benches, test cases creation, crafting assertions, ... running simulations, and achieving all coverage goals + Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the… more
- Meta (Sunnyvale, CA)
- …silicon, hardware, software, and content. The Reality Labs team seeks a Silicon Validation Engineer .As a Silicon Validation Engineer , you will be part of the RL ... effort to ensure high-quality silicon delivery. **Required Skills:** Silicon Validation Engineer Responsibilities: 1. Responsible for SoC and E2E system validation… more
- Meta (Sunnyvale, CA)
- …transistors, through architecture, to firmware, and algorithms.We are seeking aC Modeling Engineer to support C modeling and software interfaces of ML, computer ... the dedicated hardware accelerators. **Required Skills:** Hardware Accelerator Modeling Engineer Responsibilities: 1. C/C++ programming for IP modeling, algorithm… more
- ManpowerGroup (Mountain View, CA)
- Job Title: Hardware Design Engineer 5 Location: Onsite in Mountain View, CA Contract Duration: 6 to 18 months Hourly Pay: $80/hr. - $85/hr. Job Summary: The Hardware ... Design Engineer 5 will play a critical role in researching,...Minimum 10 years o Expertise in pre-Si Design Verification ( DV ) test generation techniques and their application to post-Si… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world's leading SoC's and GPU's. This position ... the future of computing. What you'll be doing: + As a Senior Verification Engineer at NVIDIA, you will be responsible for verifying the design, architecture and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization ... CDC, RDC, Synthesis, STA, Power). 11. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and Design teams to assess ... estimation tools 10. Collaborate with internal HW/SW Co-design, Architecture, Design, DV , and Emulation teams for power flows, optimization and estimation **Minimum… more