• Hardware Test Engineer

    Palo Alto Networks (Santa Clara, CA)
    …responsible for the manufacturing capabilities to build our next-generation network firewalls. As a Hardware Test Engineer ( DfT ), you will be responsible ... coverage and serviceability with ICT and boundary scan + Drive DfT and test coverage analyses from early Prototype design stages with HW/SW design engineering… more
    Palo Alto Networks (10/30/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …the implementation and post silicon validation flows. * Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, ... Jose, CA office location Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and ...development of test benches to verify comprehensive Design-for- Test ( DFT ) architecture that supports ATE screening,… more
    Cisco (10/17/24)
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  • CPU DFT Engineer

    Qualcomm (Santa Clara, CA)
    …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... engineers and test engineers to verify the DFT and...Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or… more
    Qualcomm (11/01/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    …to physical design signoff activities. What You'll Do * Responsible for implementing the Hardware Design-for- Test ( DFT ) features that support ATE, in-system ... Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for...logic & IP integration; familiarity with functional verification * DFT CAD development - Test Architecture, Methodology… more
    Cisco (11/01/24)
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  • Hardware Test Engineer INTL…

    Insight Global (San Jose, CA)
    Job Description Insight Global is seeking a experienced Test Engineer to join a large networking company in the Bay Area. You will be joining the Silicon ... Operations team focusing on ATE test bring up in the post silicon lifecycle. You...development and debug to provide insights to production and DFT . Salary expectations for this role range from $36.00-$39.00/hour… more
    Insight Global (10/24/24)
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  • Test Engineer

    Teradyne (San Jose, CA)
    …succeed within an open collaborative peer environment. Role & Responsibilities As a Test Engineer you will be responsible for defining and implementing ... manufacturing test strategy for new hardware devices. You...NPI engineers, Product Engineers to provide design for testability ( DFT ) feedback throughout the design process . Investigate and… more
    Teradyne (10/05/24)
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  • Senior DFX Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …of pattern formats, failure processing, and test program development + Knowledge of DFT security and hardware system security is a plus. + Strong programming ... We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously...and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving… more
    NVIDIA (10/11/24)
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  • Sr. Silicon ATE Engineer , Project Kuiper

    Amazon (Sunnyvale, CA)
    …around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive ... for SoCs tested on Teradyne and Advantest equipment. Convert test patterns from the DFT team into...JTAG and boundary-scan techniques. Understand of and experience with DFT and DFM. Experience with ATE hardware more
    Amazon (08/16/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …working out of the Milpitas/San Jose office location. Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's ... Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes,...in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend… more
    Cisco (10/23/24)
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  • Sr. RF Product Engineer

    Qualcomm (Santa Clara, CA)
    …Qualcomm Atheros, Inc. **Job Area:** Engineering Group, Engineering Group > Hardware Engineering **General Summary:** **Job Overview** The product engineering role ... support tasks. Fulfilling these responsibilities will involve early engagement on DFT and execution strategies, characterization of product performance across bench… more
    Qualcomm (10/30/24)
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  • Senior System Level Product Engineer

    NVIDIA (Santa Clara, CA)
    …a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to making a difference in the world through ... As a member of this team, you are responsible for developing procedures and test specs for manufacturing line with an innate understanding of product quality and… more
    NVIDIA (11/02/24)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    …our architecture and the collaborate with Quality Assurance engineers to deliver great test coverage and improve the Hardware quality. + Coordinate with internal ... Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA...Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most… more
    NVIDIA (10/16/24)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We ... craft the networking hardware for Enterprises and Service Providers, the Public Sector,...talent and vast ASIC development expertise in design, DV, DFT , physical design, and post-silicon validation The team comprises… more
    Cisco (10/28/24)
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  • SOC Design Top Level Assembly Methodologies…

    NVIDIA (Santa Clara, CA)
    …our diverse family today! The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design and methodologies. What you'll be ... improve our RTL top-level assembly process and tool set + Top-level assembly: Test new code/features and Address questions and concerns, in addition to developing… more
    NVIDIA (10/15/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …logic synthesis and verification, knowledge of Place and Route, and understanding of Design-for- test ( DFT ) is a plus. + Proficiency in scripting language, such ... We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in… more
    NVIDIA (08/31/24)
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  • ASIC Design Engineer , Cloud-Scale Machine…

    Amazon (Cupertino, CA)
    …Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine ... integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of...assertions - Have good debug skills to analyze RTL test failures - Have a "Learn and Be Curious"… more
    Amazon (10/24/24)
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  • Silicon Engineering Intern, BS/MS, Summer

    Google (Mountain View, CA)
    …a Silicon Engineer , you will design, develop and deploy consumer hardware . Google's Consumer Hardware Silicon division builds chips optimized for ... or a related technical field. + Experience with basic design concepts and computer hardware architecture. + Experience with one or more of the following: C, C++,… more
    Google (10/08/24)
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