• Senior Lead DFT Design

    Cadence Design Systems, Inc. (San Jose, CA)
    … SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). Ability to lead from DFT Architecture to Silicon Debug is required. ... Design with focus on Design for Test ( DFT ) + Should be able to lead DFT in projects from architecture to silicon debug + Should possess intimate… more
    Cadence Design Systems, Inc. (04/06/24)
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  • 3D IC Solutions Engineer- DFT Design

    Siemens Digital Industries Software (Fremont, CA)
    DFT /Test support for package and chiplet level testing of 2.5/3D IC package designs. The DFT design lead will work closely with the 3D IC solutions teams ... design . **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and high performing individual for...wafer level test planning of 3D IC chiplets. The DFT design lead will also… more
    Siemens Digital Industries Software (05/30/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design ... team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
    NVIDIA (06/15/24)
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  • Senior Post Silicon Hardware Engineer

    NVIDIA (Santa Clara, CA)
    …features. + Work closely and proactively with other engineering teams such as DFT design team, system architects, chip and board designers, software/firmware ... , maintain schedule and alignment across various teams. + Lead debug efforts from HW side to root cause...offs like cost. + Strong EE fundamentals, knowledgeable in DFT , digital design , computer architecture, power analysis,… more
    NVIDIA (05/26/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... the entire line of products. + Be a mentor/technical lead for junior team members. What we need to...verification, knowledge of Place and Route, and understanding of Design -for-test ( DFT ) is a plus. + Proficiency… more
    NVIDIA (05/08/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design -for-test ( DFT ) and logic design is a plus. + Proficiency in ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...used in next generation GPUs. + Be a mentor/technical lead for junior team members. What we need to… more
    NVIDIA (06/06/24)
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  • Senior / Lead RTL to GDSII Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …and Route, Design Closure, and timing/power signoff, RTL to GDSII. Lead technical campaigns and strategies in the RTL to GDSII digital implementation space. ... customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place...Power, Performance, and Area (PPA) Deliver technical presentations and lead discussions internally and with customers. Work closely with… more
    Cadence Design Systems, Inc. (06/22/24)
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  • Senior Silicon Hardware Development…

    NVIDIA (Santa Clara, CA)
    …silicon designs to improve quality, safety, and manufacturability. + Collaborate and Lead : Collaborate across System Architecture, DFT , ASIC, SW/FW, platform, ... validation, and production teams throughout the product life cycle; Lead system-level architecture, design , productization, debugging, and deployment. + Push the… more
    NVIDIA (04/16/24)
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  • Senior Manager, Test Engineering

    Palo Alto Networks (Santa Clara, CA)
    …experience with a deep understanding of manufacturing test + Experience with electronics system design and DfT + Experience with ICT and advanced Boundary Scan ... cybersecurity as we are. **Our Approach to Work** We lead with flexibility and choice in all of our...capabilities to build our next-generation network firewalls. As a Senior Test Manager, you will be responsible for ensuring… more
    Palo Alto Networks (06/08/24)
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  • 3D IC Solutions Engineer- Package Design

    Siemens Digital Industries Software (Fremont, CA)
    …motivated, and high performing individual for an opportunity to serve as the package design lead in our 3D IC Solutions Engineering team in driving the ... development, testing and validation of these workflows. The package design lead will also provide technical support...Virtuoso) o Physical Verification: DRC, LVS, IR/EM analysis o DFT integration and ATE test support. + Working knowledge… more
    Siemens Digital Industries Software (05/26/24)
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  • 3D IC Solutions Engineer- Technical Lead

    Siemens Digital Industries Software (Fremont, CA)
    …and system design . **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and high performing individual for an opportunity to serve ... Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around...as a technical lead of our 3D IC Solutions Engineering teams in… more
    Siemens Digital Industries Software (05/26/24)
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  • 3D IC Solutions Engineer- Thermal/Stress Engineer

    Siemens Digital Industries Software (Fremont, CA)
    …and system design . **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and hard-working individual for an opportunity to serve as ... a senior thermal/stress analysis lead in our 3D...tools and design methods including: o RTL Design /Verification, Logic Syntheses, LEC, STA analysis o DFT more
    Siemens Digital Industries Software (05/30/24)
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