- NVIDIA (Santa Clara, CA)
- …team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The ... verification methodologies. + Contribute to architecting and developing brand-new RTL analysis flows. + Serve as an...documents and train internal users. + Use data collection, analysis , and reporting tools to provide methodology … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Power Optimization and Analysis Engineer! NVIDIA prides ourselves in having energy efficient products. We believe that continuing ... NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate...internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve… more
- BAE Systems (San Jose, CA)
- …start up with the stability of a large company. We are looking for a senior level chip designer who has strong proficiency in both + ASIC design- performing ... architecture design, RTL coding/simulation, timing closure at layout phase + Verification-...+ Verification- executing testbench creation, functional coverage, test failures analysis , regression Detail requirements + Front End Design and… more
- Microsoft Corporation (Santa Clara, CA)
- …Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer - IO. You will join our front-end silicon team and be ... all employees to positively impact our culture every day. **Responsibilities** As a Senior Silicon Engineer-IO in the Data Processing Unit team you will be… more
- NVIDIA (Santa Clara, CA)
- …level. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing ... + Apply knowledge and experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS (or equivalent experience) in… more
- NVIDIA (Santa Clara, CA)
- …and VLSI? Be part of a diverse team crafting NVIDIA's chip design methodology ! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis, ... equivalence checking, and early physical design and methodology for all of NVIDIA's semiconductor products. As part...to evaluate the industry's most powerful design implementation and analysis tools. + Provide support for ASIC tools and… more
- NVIDIA (Santa Clara, CA)
- …reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design ... for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms. Key responsibilities include developing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... asynchronous checking including clock domain crossing checks and MTBF analysis , logic synthesis, netlist quality checks, etc. + Help...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more
- SpaceX (Sunnyvale, CA)
- …for test modes. + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +...and clock domain crossing flows + Deploy and enhance methodology and flows related to timing constraint generation and… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a ... - Review sign-off level timing closure using static timing analysis of various DFT modes - Contribute to wafer...during DFT implementation. - Experience in writing verilog/system verilog RTL related to DFT logic design. - Experience in… more
- NVIDIA (Santa Clara, CA)
- …+ You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing ... methodology for the next generation of designs. + Finding...chip or subsystem level with a good understanding of RTL /logic design skills as well as physical design/circuit skills… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... chip, board and system design. **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and high performing individual for an opportunity to… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Detailed knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... chip, board and system design. **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and high performing individual for an opportunity to… more