• Senior Synthesis Flow

    NVIDIA (Santa Clara, CA)
    …team, you'll design, develop and support sophisticated flows around EDA tools and our CAD programs. What you'll be doing: + You will architect highly automated and ... engineering methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs… more
    NVIDIA (11/02/24)
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  • Senior Silicon Engineer PD CAD

    Microsoft Corporation (Mountain View, CA)
    …Enhance design productivity with advanced scripting skills for development/maintenance of large CAD (Computer Aided Design) flow systems + Perform detailed ... to the future of Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer** to join our team! If you are like tackling complex Register… more
    Microsoft Corporation (10/26/24)
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  • Senior ASIC Design Engineer - Memory…

    NVIDIA (Santa Clara, CA)
    …RTL design, synthesis , functional verification and timing analysis using groundbreaking CAD tools and using the latest process technologies. What we need to see: ... We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As...have experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning,… more
    NVIDIA (08/14/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …GPU and Tegra chips and interact directly with unit-level ASIC, Physical Design, CAD , Package Design, Software, DFT and other teams. What you'll be doing: + ... in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow , and design automation. + Strong coding skills in Perl, Python,… more
    NVIDIA (10/24/24)
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  • Sr. Physical Design Methodology Engineer,…

    Amazon (Cupertino, CA)
    …in EE/CS - 5+ years of experience in developing physical design methodology or CAD flows in synthesis , PNR, and sign-off areas for advanced technology nodes. ... Define, develop and deploy innovative physical design methodologies (RTL2GDS) and CAD flows for ML Accelerator chips in advanced nodes Drive improvement… more
    Amazon (10/18/24)
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  • Sr. DDR IP Design Engineer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …IP core development and integration + Responsible for RTL design, synthesis , timing constraints, power estimation, and timing analysis using industry-leading ... CAD tools in the latest generation process technologies +...of experience working with ASICs and the VLSI design flow + Experience in RTL development and verification using… more
    SpaceX (10/21/24)
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