- NVIDIA (Santa Clara, CA)
- …methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs ... of Python, Perl , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design, formal equivalence checking. + Proven track record developing flows… more
- SpaceX (Sunnyvale, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. Synthesis & Front-End STA Engineer (Silicon Engineering) at...RESPONSIBILITIES: + Full chip and block level timing constraint development , consistent full chip and block constraint partitioning +… more
- NVIDIA (Santa Clara, CA)
- …methodology! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis , equivalence checking, and early physical design and methodology for all ... architect highly automated and customizable design software incorporating logic/physical synthesis , design planning, and equivalence checking for industry-leading chip… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …through simulations, synthesis and publications. As you grow into more senior roles, you will use your knowledge of different memory interface standards to ... make an impact on the world of technology. Title Senior Applications Engineer - DDR Design IP Job Location:...the benefit of both technical growth and business skill development . You will be part of the Technical Field… more
- NVIDIA (Santa Clara, CA)
- …protocols, interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing ... We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC...micro-architecture, implement in RTL, and deliver a fully verified, synthesis /timing clean design. + Collaborate and coordinate with architects,… more
- NVIDIA (Santa Clara, CA)
- …simulations, and/or transistor level STA as well as Experience in methodology and/or flow development /automation. The base salary range is 128,000 USD - 258,750 ... frontend and backend implementation from RTL to gds2, including synthesis , equivalence checking, floor-planning, timing constraints, timing and power convergence,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Hardware Design Engineer for our Tegra group! NVIDIA is seeking passionate Senior Hardware Design Engineers to design and verify ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis /timing clean design. + Support post-silicon validation activities working with… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Hardware Design Engineer for our Tegra group! NVIDIA is seeking passionate Senior Hardware Design Engineers to architect, design ... and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis , timing and back-end teams to accomplish your tasks. What we… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow . + Exhibit excellent communication skills and be ... + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of fundamental physical design flows and stages +… more
- SpaceX (Sunnyvale, CA)
- …engineering or computer science + 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong ... and capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg synthesis , floorplanning,… more
- SpaceX (Sunnyvale, CA)
- …core development and integration + Responsible for RTL design, synthesis , timing constraints, power estimation, and timing analysis using industry-leading CAD ... of experience working with ASICs and the VLSI design flow + Experience in RTL development and...Familiarity with Unified Power Format (UPF) for simulation and synthesis + Programming skills in C, PERL/Python + An… more
- SpaceX (Sunnyvale, CA)
- …/timing clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis , timing closure, formality check and ECOs) + Participate in ... nodes for high speed and low power consumption + Software design and development skills + Excellent scripting skills (csh/bash, Perl, Python etc.) + Experience with… more