- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- Capgemini (San Francisco, CA)
- **Job Role:** ** Physical Design (Synthesis) Engineer** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:**… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... needs aligned with customer product roadmaps. . Engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is… more