- Cisco (San Jose, CA)
- …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... chip tape out, including test coverage, STA. * Prior experience with pre-silicon DFT implementation and verification flows, and post-silicon test bring up… more
- Cisco (San Jose, CA)
- …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... custom DFT logic & IP integration; familiarity with functional verification * DFT CAD development & EDA interactions - Test Architecture, Methodology and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design For Test ( DFT ) Architect. An intimate knowledge and experience in ... highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. + Prior15+ years of professional… more
- Cisco (San Jose, CA)
- …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... DFT logic & IP integration; familiarity with functional verification * DFT CAD development - Test Architecture, Methodology and Infrastructure * Background… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- Cisco (San Jose, CA)
- …of the most complex ASICs being developed in the industry. Your Impact As an ASIC Engineering Technical Leader, you will be responsible for leading the design, ... verification , and software, to ensure alignment and resolve technical challenges. Responsibilities will include: * Leading architecture design and optimization… more
- Cisco (San Jose, CA)
- …junior engineers on performing project tasks and problem solving. * Collaborate with the verification , PD, DFT , Package and SW teams to develop next generation ... AI Switching ASIC . * Perform diagnostic and post silicon validation tests...delivering project milestones and deadlines. * Ability to communicate technical concepts to audiences spanning executives to junior engineers… more
- Cisco (San Jose, CA)
- …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification , memory designs, and physical design & DFT . Why ... you directly if a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within Cisco, including marketing, system… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience leading digital verification using SystemVerilog for ASIC designs. + Experience developing and ... and deliverables. + Work closely with system, software, design, Design for testing ( DFT ) and physical implementation stakeholders to make technical decisions. +… more
- Cisco (San Jose, CA)
- …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...Science, with 7+ year minimum of hands-on experience in ASIC implementation and Physical verification * Prior… more
- Broadcom (San Jose, CA)
- …in physical design and STA 5. Well verse in EDA tools for physical design verification and sign-off. 6. Knowledge of ASIC design flow including physical design, ... design, chip architecture, microarchitecture, Verilog RTL coding 3. Front-end logic design verification , DRC, logic synthesis 4. Knowledge of DFT methods… more
- Google (Mountain View, CA)
- …in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset. + Knowledge of ASIC Verification , DFT , synthesis, STA, or Physical Design. ... or Computer Science, with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks, reset checks and low power… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** Broadcom ASIC product division is a leader in semiconductor innovation, delivering ... micro-architecture, and design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness,… more