- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** We are looking for energetic and passionate memory design engineers to join our Central Engineering Group and be ... of process technology. **Available Job Responsibilities** + Analyze different memory architectures and highlight the tradeoffs + Design... memory architectures and highlight the tradeoffs + Design and build memory or circuit blocks… more
- General Motors (Mountain View, CA)
- …application selection, technical reviews, and sourcing phases. + Spearhead SoC & memory selection and design applications around the selected components meeting ... applications. This role is specifically for a staff hardware engineer with a strong focus on System on a...design and development + Understanding of SoC architecture, memory hierarchy, and ASIC design flow +… more
- Teradyne (San Jose, CA)
- …testers for the DRAM and FLASH memory market. As a Hardware Circuit design Engineer , you will be responsible for the concept-through-production design of ... of dedicated, enthusiastic, and dynamic team players in the Memory Tester' Business Unit. Here, we design ...will have 5+ years of experience as a circuit design engineer , with experience designing digital and… more
- Micron Technology, Inc. (San Jose, CA)
- …be responsible for crafting the on-chip memory controller, for non-volatile memory products, design validation at block, subsystem, and fullchip level. ... **Responsibilities and Tasks** _Contribute to the Development of New Memory Products by owning the overall logic design... Memory Products by owning the overall logic design of the on-chip memory controller, including… more
- Microsoft Corporation (Mountain View, CA)
- …and-ultimately-making a difference in the world. We are looking for a **Fabric IP Design Engineer ** to join the team. **Growth Mindset** We fundamentally believe ... Cloud Compute Development Organization is seeking a **Fabric IP Design Engineer ** to join our IP development...this role, you will: + Be part of a design team developing advanced components of the memory… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + ... the device. This candidate needs strong debugging skills to design and create solutions to challenging memory ...to design and create solutions to challenging memory interface issues. Candidate will work closely with applications… more
- Celestica (San Jose, CA)
- …States State/Province: California City: San Jose **Summary** The **Senior Staff Engineer , Electrical Design ** develops innovative electrical systems and circuits ... they design . Collaboration is key, as the Senior Staff Engineer works in cross-functional teams with designers, customers, manufacturing engineers, and project… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Senior Principal Design Engineer - Systems and Interfaces San Jose Job Description: The Cadence ... CSG Central Applications Engineering team seeks an experienced SoC design engineer to integrate and support Cadence...tools to integrate and validate reference designs using compute, memory , and interface IP components. The members of the… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture and ... micro-architecture of digital subsystems + RTL design of digital circuits using Verilog + Frontend ...of large ASIC designs including: Integration of Processors, Bus, Memory , and Interface IPs + Chip level integration and… more
- Microsoft Corporation (Mountain View, CA)
- …servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... yourself as an integral member of a digital logic design team for the development of AI components with...in one or more of the following: + High-performance memory subsystems and multi-level caches + System knowledge (software/firmware/hardware… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... including micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance...the following are highly desired + ARM CPUs + Memory controllers + Peripherals such as I2C, SPI and… more
- Microsoft Corporation (Mountain View, CA)
- …cloud servers, clients, and augmented reality. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... day. **Responsibilities** + You will be part of the design team driving many facets of high performance, high...variety of micro-architecture areas such as Complex Control Paths, Memory hierarchies and standard industry interfaces such as Advanced… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...in data path development 15. Experience in CPU, NOC, Memory and Peripheral Subsystems 16. Experience in HLS 17.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...in data path development. 9. Experience in CPU, NOC, Memory and Peripheral Subsystems. 10. Experience with Synthesis, Timing… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...path development 11. Experience in CPU, Network protocols, NOC, Memory and Peripheral Subsystems 12. Experience with Synthesis, Timing… more
- Cisco (San Jose, CA)
- …hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various ... in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend...experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. * Prior experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Digital IP (Intellectual Property), from RISC-V processor cores to DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are ... work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are...Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …platform that can emulate multi-Billion gate designs with very high amount of memory while maintaining the scalability of the usage modes and debug tools. The ... power devices into complex scalable enterprise grade hardware. The design / verification / physical design of these ASICs pushes various tools to their limits.… more
- Microsoft Corporation (Mountain View, CA)
- …Logic Engineer ** with experience in high performance Dynamic Random-Access Memory (DRAM) memory controllers and DDR4/5 PHYs. Microsoft's mission is to ... worldwide and we are looking for a **Principal Logic Engineer ** to help achieve that mission. As Microsoft's cloud...day. **Responsibilities** + Microarchitect major blocks of a DRAM Memory Controller and implement the design with… more
- Broadcom (San Jose, CA)
- …Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes ... designs. + Experience with external customer support for design IPs or VIPs. + Expertise in System Verilog especially writing SVAs for formal. Familiar with… more