- Tarana Wireless (Milpitas, CA)
- …+ Work with some of the best DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level + Build and ... continuously improve verification infrastructure and methodologies to meet the demands of...RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project… more
- Cisco (San Jose, CA)
- …Who You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of ... ASIC design verification experience. * Proficient in ASIC verification using UVM/System Verilog. * Proficient in verifying complex blocks, clusters and… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- Qualcomm (San Jose, CA)
- …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design, optimize, verify, validate, implement, ... Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related work experience. OR… more
- Cisco (San Jose, CA)
- …the world What You'll Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer /lead to engage in new development of our UCS ... Bachelor's or Master's degree in equivalent experience. * Prior experience with ASIC verification using UVM/System Verilog. * Prior experience verifying complex… more
- Google (Mountain View, CA)
- Senior Mixed-Signal ASIC Designer, Project Taara...About the role: The Taara Project is seeking a Senior Integrated Circuit engineer leading the next ... systems. The successful candidate will lead application specific integrated circuit ( ASIC ) development from concept to product. The position seeks highly-motivated… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + ... high-speed design concepts + Participate in design, architecture, and verification reviews + Cover digital backend design from synthesis,...route netlists + Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …leaders and innovators who want to make an impact on the world of technology. Senior Principal Design Engineer - Systems and Interfaces San Jose Job Description: ... Systems Group (CSG) develops and licenses IP designs for SoC and ASIC systems. This includes high-performance DSPs, CPUs, Interface IP, DDR controllers, hardware… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial ... Intellectual Property (IP) + Silicon validation + Collaborate with the verification team to ensure the implementation meets both architectural and… more
- Capgemini (San Jose, CA)
- **Job Role: Senior ** **Performance Modeling Engineer ** **Job Location: San Jose CA** **Job description:** We are seeking a highly skilled candidate with a strong ... + Experience with Synopsys or Cadence EDA tools and ASIC /SOC Power Analysis Tools. + Deep understanding of SoC...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...implementation of blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. .… more
- Microsoft Corporation (Mountain View, CA)
- The Artificial Intelligence Silicon Engineering team is seeking a ** Senior Validation Engineer ** to deliver premium-quality designs once considered impossible. ... an extremely efficient manner. We are looking for a ** Senior Validation Engineer ** to work in the...post silicon functional validation of complex Application Specific Integrated Circuits( ASIC ) System on Chip (SOC). + Define testing strategies… more
- Teledyne (Mountain View, CA)
- …and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design of integrated circuits ... reviews, and participates in design implementation. Responsibilities include debugging, verification , and resolving technical issues, innovating intellectual property, developing… more
- Cisco (San Jose, CA)
- …Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. ... test, debug and diagnostics needs of the design. * Work closely with the design/design- verification and PD teams to enable the integration and validation of the Test… more
- Actalent (Mountain View, CA)
- …5 YOE: Tests, Tools and Automation development Summary: We are looking for Senior Silicon Validation Engineer to work in the dynamic Artificial Intelligence ... the Role Purpose of the Team: The purpose of this team is : FPGA Design Verification , System level debug, Filing bugs The role will consist of: + Very few meetings… more
- Actalent (Mountain View, CA)
- Silicon Validation Engineer - Mountain View, CA Summary: We are looking for Senior Silicon Validation Engineer to work in the dynamic Microsoft Artificial ... team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are… more