- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- Amazon (Cupertino, CA)
- …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- Amazon (Cupertino, CA)
- …we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze ... - BS + 4yrs or MS + 3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and route,… more
- Broadcom (San Jose, CA)
- …already have a Candidate Account, please Sign-In before you apply.** **Job Description:** The ASIC Design Engineer will need to interact internally with the ... manufacturing yield. The candidate should have a strong understanding of VLSI and ASIC physical design 20+ years of experience w/ a deep understanding of… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon ... ASIC engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Design Responsibilities: 1. Participate in… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... to stand out from the crowd: + Pipeline processor or deep learning accelerator design /architecture experience + Low power or physical (synthesis/VLSI) design … more
- Meta (Sunnyvale, CA)
- …build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in Design Implementation, ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our...efficiently. You will have an opportunity to participate in design implementation/emulation, physical design , EDA… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
- Google (Mountain View, CA)
- ASIC Lead Engineer , Project Taara (Fixed Term) Hardware Engineering Mountain View, CA This is a fixed-term contract position for 12 months About the team: At X ... About the Role: The Taara Project is seeking an ASIC lead engineer to drive the next...input from various teams, contribute to the detailed circuit design , own the foundry submission process, oversee physical… more