• Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
    SpaceX (11/15/24)
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  • Senior ASIC Physical Design

    Capgemini (Santa Clara, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
    Capgemini (10/16/24)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
    NVIDIA (12/19/24)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
    NVIDIA (12/25/24)
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  • ASIC Engineer , Physical

    Meta (Sunnyvale, CA)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
    Meta (10/22/24)
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  • ASIC Physical Design

    Amazon (Cupertino, CA)
    …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
    Amazon (10/04/24)
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  • ASIC Digital Physical Design

    Broadcom (San Jose, CA)
    …in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design or PhD in Electrical Engineering or Computer Engineering with ... 7+ years of experience in Physical design . + Deep knowledge about industry standards in Physical Design , Physical aware synthesis, Floor-planning,… more
    Broadcom (11/22/24)
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  • Physical Design Engineer

    Amazon (Cupertino, CA)
    …we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze ... - BS + 4yrs or MS + 3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
    Amazon (11/01/24)
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  • Sr. Physical Design Methodology…

    Amazon (Cupertino, CA)
    …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and route,… more
    Amazon (10/18/24)
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  • Senior ASIC Floorplan Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
    NVIDIA (11/06/24)
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  • ASIC Engineer Intern, Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon ... ASIC engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Design Responsibilities: 1. Participate in… more
    Meta (11/02/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also… more
    Cisco (11/15/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also… more
    Cisco (11/08/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation… more
    Cisco (10/28/24)
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  • ASIC Design Verification…

    Palo Alto Networks (Santa Clara, CA)
    …is to create an environment where we all win with precision. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ... equivalent military experience required - MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking ASIC more
    Palo Alto Networks (12/06/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design more
    NVIDIA (11/05/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …verified. You will work closely with Back-end team on timing signoff for seamless physical design closure. You will also collaborate with the System and Software ... Engineering, Computer Science or related degree with 5+ years of ASIC design experience or Masters degree in Electrical Engineering, Computer Science or… more
    Cisco (11/27/24)
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  • ASIC Packaging Engineer

    Meta (Menlo Park, CA)
    …Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 6. ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Mechanical/Thermal modeling focus...ASIC R&D and manufacturing to drive the mechanical/thermal design using advanced FEA of new ASICs, and make… more
    Meta (11/14/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design more
    NVIDIA (10/22/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design more
    NVIDIA (10/22/24)
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