• CPU Systems RTL Engineer

    Qualcomm (Santa Clara, CA)
    … Engineering **General Summary:** We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, ... in Computer or Electrical Engineering with 5+ years of CPU RTL or similar experience. * Thorough...Configuration access protocols, RAS and safety aspects, AMU/PMU architecture, Power management architectures - Active and Idle… more
    Qualcomm (06/04/24)
    - Save Job - Related Jobs - Block Source
  • CPU Design Manager, Silicon

    Google (Mountain View, CA)
    …or equivalent practical experience. + 10 years of experience in high-performance CPU or AI accelerator logic/ RTL design including micro-architecture definition ... bonus, equity, or benefits. Learn more about benefits at Google. + Develop CPU subsystem front-end designs, emphasizing micro-architecture and RTL design for the… more
    Google (08/02/24)
    - Save Job - Related Jobs - Block Source
  • Hardware ( CPU , GPU, SoC, Digital Design,…

    Qualcomm (Santa Clara, CA)
    …+ Experience with system-level performance modeling and simulation + Knowledge of power management techniques and strategies + Experience with thermal analysis ... one of the following Qualcomm multi-disciplinary teams: System (architecture, modeling, power , thermal as well as silicon profiling ), Front-end Design… more
    Qualcomm (08/20/24)
    - Save Job - Related Jobs - Block Source
  • Silicon Validation Engineer

    Meta (Sunnyvale, CA)
    … architecture, memory subsystems, Cache hierarchies, SoC integration flows and UPF based power management 13. Solid understanding of SoC architecture and Pre-Si ... able to debug through layers of SW applications to RTL FSDBs 3. Map Protocol Checkers, RTL ...scenarios on the Pre-Si platforms and generate data for Power & Performance of different IP Blocks 5. Bring-up… more
    Meta (07/19/24)
    - Save Job - Related Jobs - Block Source
  • Senior ASIC Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    …What you'll be doing: + Drive physical design and timing of high-frequency and low- power CPU , GPU, DPU and SoCs at block level, cluster level, and/or ... level. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing… more
    NVIDIA (06/19/24)
    - Save Job - Related Jobs - Block Source
  • Senior GPU Memory Architect

    NVIDIA (Santa Clara, CA)
    …micro-architecture to improve the state-of-the-art in GPU memory system and memory management optimizing along the axes of performance, power efficiency, ... in solving complex problems while optimizing performance, area, complexity, and power on leading-edge silicon processes. This GPU memory architecture team creates… more
    NVIDIA (07/25/24)
    - Save Job - Related Jobs - Block Source
  • Senior System Architect, Hardware Architecture

    Amazon (Sunnyvale, CA)
    …video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management , system performance benchmarking, etc. As part of ... video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management , system performance benchmarking, etc. * Hands-on… more
    Amazon (07/28/24)
    - Save Job - Related Jobs - Block Source
  • Machine Learning SoC Architect

    Meta (Menlo Park, CA)
    …with higher performance and lower energy consumption as compared to running them on the CPU /GPU of the server. This is a architect role in which you will be defining ... computation throughput, memory bandwidth and latency 3. evaluate performance v/s area v/s power tradeoffs. 4. Drive the architecture definition of one or more of the… more
    Meta (08/14/24)
    - Save Job - Related Jobs - Block Source
  • Senior ASIC Engineer, Timing

    NVIDIA (Santa Clara, CA)
    …What you'll be doing: + You will drive physical design of high-frequency and low- power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with ... design, such as driving timing convergence, timing constraints generation and management , and ECO generation and implementation. + Work in a cross-functional… more
    NVIDIA (07/27/24)
    - Save Job - Related Jobs - Block Source
  • SoC Architect

    Meta (Sunnyvale, CA)
    …with higher performance and lower energy consumption as compared to running them on the CPU /GPU of the server. This is an architect role in which you will be ... throughput, memory bandwidth and latency, evaluate performance v/s area v/s power tradeoffs. 3. Identify appropriate workloads and micro-benchmarks to be used… more
    Meta (07/27/24)
    - Save Job - Related Jobs - Block Source