- Google (Sunnyvale, CA)
- …sign-off for ASICs. Preferred qualifications: + 12 years of experience in the domain of physical design and static timing analysis. + Experience leading one ... equivalent practical experience. + 5 years of experience in static timing (ie, to create full chip timing constraints,...timing ECO creation). + Experience in working across various physical design areas (ie, EDA scripting, block… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- Google (Mountain View, CA)
- …convergence including Static timing analysis (STA), electrical checks, and physical verification. + Experience in package design and signal/power integrity ... in the area of Application Specific Integrated Circuit (ASIC) physical design as we realize sophisticated electronics...floor planning, place and route, Clock Tree Synthesis (CTS), Design For Test (DFT) (Scan, MBIST, BISR), Static… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …years of experience. Master's degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is ... an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description +...support is a plus + Experience in DFT or physical design is a plus + Experience ... , architecture, and verification reviews + Cover digital backend design from synthesis, static timing and logic...+ Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a **Silicon** ** Design Engineer ** **2** to work on leading edge custom IP development as ... of IP blocks, working with a group of other design team members, as well as design ...working on defining microarchitecture specifications, developing RTL, and running static checks, synthesis, and timing analysis. Embody our Culture… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
- NVIDIA (Santa Clara, CA)
- …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Passionate about SW development processes ... design technologies such as CoWoS-L. As a software engineer , you will craft highly efficient software to automate...C++, compiler, build systems, and database. + Experienced with static and dynamic code analysis tools The base salary… more
- NVIDIA (Santa Clara, CA)
- …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Flexibility/adaptability for working in a ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …block and Chip top level You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon ... RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts. Knowledge of the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
- NVIDIA (Santa Clara, CA)
- …circuits for hardware security, adaptive clocking and power management solutions + Drive the design and physical implementation of custom digital IPs from RTL to ... impact on the world! What you'll be doing: + Participate in ground breaking Processor design in deep submicron technologies. + Work as part of a global circuits team… more
- Snap Inc. (Palo Alto, CA)
- …pair of glasses that bring augmented reality to life. We're looking for a Staff FEA engineer to join the Snap Lab team at Snap Inc! What you'll do: + Provide ... for Snap Lab's structural engineering analysis efforts. + Perform static and dynamic structural simulations using Abaqus _(preferred)_ or...who may assist in simulation tasks or testing of physical parts. + Lead and coordinate with partner teams… more
- Siemens Digital Industries Software (Fremont, CA)
- …Engineering, or other related fields. + Minimum of 5 year's experience of design , static timing analysis, and Tcl/Python scripting + Software Engineering skills, ... + Knowledge and understanding of all aspects of a design flow - particularly SDC, static timing...creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability unrelated to ability, marital status,… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of ... Work hard. Have Fun. Make history. At Amazon, DFT ( Design -for-Testability) is a multi-faceted job that involves architecture definition,...patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction. + Good understanding of Cadence ... Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should… more
- Ross Stores, Inc. (Dublin, CA)
- …procedures and protocols to ensure integrity and compliance\. The Network Security Engineer leads the product area strategy, roadmap, design , and vendor/product ... and development for our teams\. **GENERAL PURPOSE:** The Network Security Engineer III is responsible for thinking strategically, envisioning, and taking steps… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Solution product. Genus is a complete product that encompasses logic synthesis and physical design . The product breadth means we are looking for skilled ... to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on… more
- Meta (Sunnyvale, CA)
- …for Power, Performance, and Area 17. 2. Floor Planning and Placement 18. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 ... "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/ physical synthesis using advanced… more