- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- NVIDIA (Santa Clara, CA)
- …optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and ... you'll be doing: + You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
- BAE Systems (San Jose, CA)
- …on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO Career Site Equal Opportunity Employer. ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...chip designer who has strong proficiency in both + ASIC design- performing architecture design, RTL coding/simulation, timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- Amazon (Sunnyvale, CA)
- Description As a Sr. ASIC Design Engineer , you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... and design hardware accelerator IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional SOC development activities - Work with the… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. FPGA/ ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer , DDR IP (Silicon...development and integration + Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing . + Good knowledge of extraction, device physics, STA methodology and… more
- SpaceX (Sunnyvale, CA)
- …front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...understanding of their impact on synthesis, physical design and timing closure + Deep understanding of ASIC … more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...for high coverage on silicon - Review sign-off level timing closure using static timing analysis of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer ! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and ... tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 10 years experience in ASIC physical design flows and methodologies in advanced process nodes. + Experience ... with ASIC physical design, physical design flows and methodologies (ie,...at Google (https://careers.google.com/benefits/) . + Lead the effort for timing closure of blocks, subsystems, and fullchip. + Drive… more
- Microsoft Corporation (Santa Clara, CA)
- …Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer - IO. You will join our front-end silicon team and ... for all employees to positively impact our culture every day. **Responsibilities** As a Senior Silicon Engineer -IO in the Data Processing Unit team you will be… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Looking for Lead SoC/ ASIC Digital Design Engineer with experience in Design for Test (DFT). Ability to ... Requirements; + Prior 15-20 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test...of JTAG 1149.1/6, IEEE1500 and IEEE1687 + Knowledge of timing analysis and equivalency checks would be added bonus… more