- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more
- Google (Mountain View, CA)
- …ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon ... a must. The Role: We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have… more
- NVIDIA (Santa Clara, CA)
- …industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams with advanced implementation ... experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools... methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- Broadcom (San Jose, CA)
- …**Job Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...range of products that keep the globe connected. Our ASIC products division is looking for senior ,… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... we're building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews.… more