- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial ... Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc. + Timing closure of high-performance digital Intellectual Property (IP) + Silicon validation +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal Integrity Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI model correlations using lab measurements to improve modelling tool/ methodology . + Package substrate and board layout SI design...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and ... with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- Amazon (Sunnyvale, CA)
- …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more