• SoC Infrastructure IP

    Qualcomm (Santa Clara, CA)
    …definition or Hands-on RAS design/verification is a plus + Strong knowledge in SOC infrastructure IP (NOC, Caches, SMMU, Memory Controller, Interrupt ... group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System...localize failure in the field + Strong knowledge in SOC and Infrastructure IP (NOC,… more
    Qualcomm (11/21/24)
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  • Senior Hardware SoC Architect

    NVIDIA (Santa Clara, CA)
    systems architects and deep learning experts to define the next generation SoC ? NVIDIA is developing processor and system architectures that are at the ... We are looking for a Senior Hardware SoC Architect for our Tegra Team! Do you...position requires an interest in reset and boot-related chip-level infrastructure domains in SOCs. It will also require a… more
    NVIDIA (10/15/24)
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  • Silicon Test Engineer, SoC , Platforms

    Google (Sunnyvale, CA)
    …test development and repair scheme implementation, including BISR/BIRA. + Experience Testing Internet Protocols ( IP ) such as Phase-locked Loops (PLL), Production ... focus on TPU architecture and its integration within AI/ML-driven systems . Google's data centers are the most advanced in...the world. In this role you will help build System on a Chips ( SoC ) that power… more
    Google (12/21/24)
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  • Principal Memory Controller Architect

    Microsoft Corporation (Sunnyvale, CA)
    …and validation teams, to productize new features. + Work with vendors to evaluate intellectual property ( IP ) and make recommendations for integration. + ... with various teams, including product and platform architecture, peer System on Chip ( SoC ) architects, IP...systems . We are committed to delivering advanced, custom SoC designs capable of performing complex and high-performance functions… more
    Microsoft Corporation (12/18/24)
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  • Senior Power & Performance Engineer

    Microsoft Corporation (Sunnyvale, CA)
    …the stack. + Develop power and performance modeling methodology by creating and owning System on Chip ( SOC ) architectural power models. + Project and report ... team to incorporate low power design methodologies and power saving techniques. Identify IP / SOC power saving opportunities and drive definition of power saving… more
    Microsoft Corporation (12/07/24)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    … organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip ( SoC ) for data center applications.As a ... verification plans, build verification test benches to enable block/ IP /sub- system / SoC level verification 2. Develop...or SVN 16. Experience with verification of ARM/RISC-V based sub- systems or SoCs 17. Experience with IP more
    Meta (11/20/24)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    … organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip ( SoC ) for data center applications.As a ... verification plans, build verification test benches to enable IP /sub- system / SoC level verification. 2. Develop...Networking designs. 17. Experience with verification of ARM/RISC-V based sub- systems or SoCs. 18. Experience with IP more
    Meta (11/05/24)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    … organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip ( SoC ) for data center applications.As a ... verification plans, build verification test benches to enable IP /sub- system / SoC level verification. 2. Develop...or SVN. 18. Experience with verification of ARM/RISC-V based sub- systems or SoCs. 19. Experience with IP more
    Meta (10/18/24)
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  • Senior Cloud Platform Architect

    Cadence Design Systems, Inc. (San Jose, CA)
    …are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our ... with industry security standards such as GDPR, HIPAA, PCI, SOC 2, and ISO 27001, working closely with the...end -to- end cloud services from the ground up. Infrastructure as Code ( IaC ) : Proficiency in… more
    Cadence Design Systems, Inc. (10/19/24)
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  • Memory Sub- System Performance Architect

    Qualcomm (Santa Clara, CA)
    …processing transformation to help create a smarter, connected future for all. The infrastructure IP Team consists of a multi-disciplinary group involved in the ... definition and design of Platform infrastructure HW components such as Memory controllers, ... Performance using cycle-accurate/approximate models and support both Infra IP level u-architecture optimizations as well as System more
    Qualcomm (11/16/24)
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  • System and Security Engineer

    Ivalua (Fremont, CA)
    …(IIS), Networking (DNS, DHCP, TCP/ IP , Routing, Firewall, WAN, etc.), NT File System , Group Policy, RDS,SSL/TLS protocols. SOC tools: SIEM & EDR. Endpoint ... Our IT team is dedicated to manage the IT Infrastructure , Cloud computing needs and the Cloud infrastructure...scope (mainly as backup of the primary US based SOC analyst) + Assist with system builds… more
    Ivalua (12/16/24)
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  • ASIC Engineer, Power

    Meta (Sunnyvale, CA)
    …Frequency Scaling(DVFS), AVS 16. Experience architecting systems for various design scales ( IP blocks, SOC , multi-chip system ) with an understanding of ... Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level. We are...around EDA tools, and low-power design to build efficient System on Chip ( SoC ) and IP more
    Meta (10/12/24)
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  • ASIC Engineer, DFT

    Meta (Sunnyvale, CA)
    …methodologies, implementation, and verification to build best-in-class System on a Chip ( SOC ) and IP for data center applications. We are looking for ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT)...in Design for Testability (DFT) methodologies and implementation for IP / SOC , with a deep understanding of Siemens/Synopsys… more
    Meta (10/18/24)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ( SoC ) and IP for data center applications. ... Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience...drive execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and… more
    Meta (10/22/24)
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  • ASIC Engineer, Emulation

    Meta (Sunnyvale, CA)
    …emulation. 15. Experience in architecting emulation systems for various design scales ( IP blocks, SOC , multi-chip system ) with an understanding of ... **Summary:** Meta is hiring ASIC Emulation Engineers within our Infrastructure organization. We are looking for individuals with experience...experience in HW emulation and prototyping required to build System on Chip ( SoC ) and IP more
    Meta (10/17/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …skills to implement the testing infrastructure to validate new core IP or SoC implementations. You will work closely with researchers, architects ... SystemVerilog, C/C++ based verification and UVM methodology. 9. 3+ years experience in IP /sub- system and/or SoC level verification based on SystemVerilog… more
    Meta (11/13/24)
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  • Digital Design Engineer

    Broadcom (San Jose, CA)
    …8+ years of experience in digital front-end design, with a focus on complex IP or SoC design or Master's degree in Electrical Engineering, Computer Engineering, ... design optimization to drive the development of high-performance digital systems for our next-generation products. As a Staff Digital...in digital front-end design, with a focus on complex IP or SoC design. + **Technical Expertise:**… more
    Broadcom (12/18/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …SystemVerilog/UVM methodology and/or C/C++ based verification. 11. 10+ years experience in IP /sub- system and/or SoC level verification based on SystemVerilog ... vendor netlists. 4. Implement scalable power aware simulation and gate level simulation infrastructure leveraging test benches in System Verilog. 5. Keep track… more
    Meta (10/18/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …SystemVerilog, C/C++ based verification and UVM methodology. 10. 5+ years experience in IP /sub- system and/or SoC level verification based on SystemVerilog ... and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to… more
    Meta (10/18/24)
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  • ASIC Engineer, Design

    Meta (Menlo Park, CA)
    …one or more of the key areas required to build successful world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer, Design ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class… more
    Meta (12/11/24)
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