- Google (Sunnyvale, CA)
- …AXI) and scripting languages (ie Tcl, Python or Perl). + Experience in UPF for low-power design , including power intent specification, verification, and ... this role, you will join a team working on SoC -level RTL design for our data center...data paths. + Develop and maintain Unified Power Format ( UPF ) specifications for power management of the design… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a Principal SOC Design Engineer to work in the dynamic Microsoft Artificial ... work and beyond. We are looking for a **Principal SoC Design Engineer ** to join...5+ years of experience with Synthesis, Timing constraints and UPF + Experience with industry standard interfaces such as… more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
- Meta (Sunnyvale, CA)
- …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design … more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... of enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... to optimize RTL code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD in Electrical Engineering,… more
- Meta (Sunnyvale, CA)
- **Summary:** We are currently seeking a machine learning performance modeling engineer to support the development of a custom machine learning software/hardware ... software and SoCs for AR/VR devices. **Required Skills:** Performance Modeling Engineer Responsibilities: 1. Lead power and performance modeling of IP components… more