- Broadcom (San Jose, CA)
- …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... our HBM, DDR and SerDes designs through comprehensive Design for Test ( DFT ) verification strategies. You will work collaboratively with cross-functional teams to… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow...You'll Do * Responsible for implementing the Hardware Design-for-Test ( DFT ) features that support ATE, in-system test, debug and… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... resident expert in areas such as physical design, STA, DFT , and packaging? Have you taped out so many...logic design verification, DRC, logic synthesis 4. Knowledge of DFT methods including scan, boundary scan, memory BIST and… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow...physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more
- Cisco (San Jose, CA)
- …designs, custom library development (Standard Cell and I/O), physical design & DFT , Signal Integrity, and complexed packaging technology. Our silicon is developed ... processing, high-speed logic design & verification, memory designs, and physical design & DFT . Why Cisco #WeAreCisco, where each person is unique, but we bring our… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career ... with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence CheckingPrior experience with Cadence tools such as… more
- Insight Global (San Jose, CA)
- Job Description Insight Global is seeking a experienced Test Engineer to join a large networking company in the Bay Area. You will be joining the Silicon Operations ... will have experience in development and debug to provide insights to production and DFT . Salary expectations for this role range from $25-28/hour We are a company… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …excited to welcome highly talented hardware design leaders/managers and application engineer leaders/managers to join our Cadence North America Field Applications ... with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence Checking + Prior experience with Cadence tools such… more
- Teradyne (San Jose, CA)
- …succeed within an open collaborative peer environment. As a Hardware Test Engineer you will be responsible for defining and implementing manufacturing test strategy ... to ensure products are built free of manufacturing defects. + Understanding of DFT (Design for Test) and DFM (Design for Manufacturing) method a plus Preferred… more
- Power Integrations (San Jose, CA)
- Senior Test Engineer Location: San Jose, CA, United States Type of Employee: Full Time Job Description: + Designs develops and implements cost-effective testing ... products. + Work with IC design team to understand design specifications and DFT proposals. + Create test programs in C language, debug and validate silicon… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... flow. * Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST. * Prior working experience with… more
- Broadcom (San Jose, CA)
- …AXI, AHB) and memory interfaces. + Understanding of low-power design techniques and DFT methodologies is a plus. + **Soft Skills:** + Strong analytical and ... problem-solving skills with meticulous attention to detail. + Effective communication and collaboration skills to work seamlessly across teams. + Ability to manage complex tasks and meet deadlines in a dynamic environment. **Preferred Qualifications:** +… more
- Cisco (San Jose, CA)
- …on performing project tasks and problem solving. * Collaborate with the verification, PD, DFT , Package and SW teams to develop next generation AI Switching ASIC * ... Perform diagnostic and post silicon validation tests in the lab. * Work with hardware and software teams to triage and root cause system, software, and customer failures. Minimum Qualifications: * Bachelor's degree in Electrical or Computer engineering and 15+… more
- Broadcom (San Jose, CA)
- …Physical Design is desirable - Basic understanding of Clock structures, Power optimization, DFT - Exposure to Tapeouts would be a plus - Must have hands-on ... knowledge of scripting in TCL/PERL/Python - Excellent verbal and written communication, presentation skills **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $91,000 - $162,000. This position is… more
- Broadcom (San Jose, CA)
- …Good understanding of memory behavioral and physical models + Good understanding of DFT schemes and chip level integration + Familiar with test setups, silicon ... testing and debug + Proficient in running simulators, writing automation scripts, and are tools savvy + Good communication, interpersonal, and leadership skills + Motivated, self-driven and good at multi-tasking **Qualifications** Requires a BS in Electrical… more
- Cisco (San Jose, CA)
- …outstanding talent and vast ASIC development expertise in design, DV, DFT , physical design, and post-silicon validation The team comprises micro-architects, ... front-end designers, and verification engineers. Cisco is a system company, so you can also use the ASIC to work with the System and Software teams and participate in the journey from sample arrival through system validation to first customer shipments. What… more
- Cisco (San Jose, CA)
- …concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. * Option to also do… more