- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...power management. 4. Hands-on experience in physical design and STA 5. Well verse in EDA tools for physical… more
- Broadcom (San Jose, CA)
- …timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and how they affect the ... Ability to understand and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF modeling of variation - MIS - multi input switching… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Cisco (San Jose, CA)
- …sign off checklist and reviews for chip tape out, including test coverage, STA . * Prior experience with pre-silicon DFT implementation and verification flows, and ... post-silicon test bring up procedures. Preferred Qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure * Post silicon validation using DFT patterns. Why Cisco? #WeAreCisco, where each person is unique, but we bring our… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …desire and ability to work in a fast-paced startup environment. + Expert in STA , Synthesis or QOR improvement techniques in the FPGA prototyping or EDA field. The ... annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …design flow. Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint and CDC ... tool flows. + Exposure to some major IP and protocols, such as SERDES, PCIe and DDR4. + Self-driven. Good communication, organization, analytical, presentation and people skills. The annual salary range for California is $131,600 to $244,400. You may also be… more
- Broadcom (San Jose, CA)
- …+ Expertise in micro-architecture design and PPA trade-offs. + Experience in synthesis, STA , and timing closure using tools like Synopsys DC or Cadence Genus. + ... Working knowledge of CDC/RDC analysis and debugging using tools such as Spyglass, Questa CDC, or similar. + **Knowledge Areas:** + Solid understanding of digital design fundamentals such as pipelining, FSMs, clock domains, and data paths. + Familiarity with… more
- Cisco (San Jose, CA)
- …concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more