- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …or related experience * Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working ... from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Broadcom (San Jose, CA)
- …DDR memory system development and debug is required. Expertise in HBM, DRAM manufacturing test and in-system DRAM test is also desirable. This position is ... DDR memory interfaces including the PHY, controller and embedded test capability. Direct experience with HBM memory is a...technology and ASIC design flow including Verilog simulation and timing analysis. Verilog experience is a plus. * Experience… more
- Broadcom (San Jose, CA)
- …complex and cutting edge network switching ASIC DFx (Design for Test /debug & manufacturability) from DFT architecture, to implementation, verification, timing ... aggressively deliver low DPPM's, while optimizing the cost for test . Responsibilities + Drive the test quality...plus + Experience or familiarity in back-end chip design, Timing , CDC flows is a plus + Strong Pre/Post… more
- Broadcom (San Jose, CA)
- …with verification engineers and physical design teams to ensure functional correctness, timing closure, and overall design robustness, with a strong focus on ... specifications, focusing on efficient and robust design implementations. **Synthesis and Timing Closure:** + Perform synthesis and work with physical design teams… more
- Arrow Electronics (San Jose, CA)
- … Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/ Test ) handling, block and top level static timing analysis, ECO ... generation at top level, handshaking with blocks for timing /functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power… more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition including micro-architecture ... crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure + Collaborate with physical design… more
- Teradyne (San Jose, CA)
- We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, ... Teradyne's test technology ensures your device works right the first...with our customer base. We are seeking an Electrical Engineer for our Nextest division to develop and maintain… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **R&D Staff Engineer ** The ideal candidate will have expertise in integrated-circuit process ... device fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure mechanisms and testing,… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design ... for test , floorplanning, place and route, clock methodology, power planning...place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. Participate… more
- Cisco (San Jose, CA)
- …implement and get it verified. You will work closely with Back-end team on timing signoff for seamless physical design closure. You will also collaborate with the ... you to: * Author micro-architecture specifications and participate in specification and test plan reviews. * Architect and implement complex RTL designs. * Scope… more