- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer...and CMOS solid state physics + Knowledge of CMOS digital design principles, basic standard cells their ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... candidate should have a high aptitude for floor-planning the design of complex digital top level and/or...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching...develop innovative technology, and to power a more inclusive, digital future for everyone. How do we do it?… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer**... and software to support the convergence of the physical and digital worlds. Coupled with the ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- Google (Sunnyvale, CA)
- …or PhD in Electrical Engineering or Computer Science. + 4 years of experience in digital / ASIC design using SystemVerilog or RTL. + Experience in one or ... equivalent practical experience. + 2 years of experience in Digital design using SystemVerilog RTL. Preferred qualifications:...and debug design RTL. + Work with physical design teams to ensure design… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which ... Engineering or related engineering fields 11. Experience with Lint, Synthesis, Formal or Physical Design tools 12. Scripting capability with Python or Perl 13.… more
- NVIDIA (Santa Clara, CA)
- …System-Verilog, with a good understanding of Computer Architecture and Digital Systems design . + A deep understanding of ASIC design flow including ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design...synthesis/timing clean design while working with the physical design team to ensure a routable… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
- Meta (Sunnyvale, CA)
- …**Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in Design Implementation, Physical Design , and Design ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization....efficiently. You will have an opportunity to participate in design implementation/emulation, physical design , EDA… more
- Amazon (Cupertino, CA)
- …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis,...Spice Circuit analysis - Experience with Place and Route, digital implementation - Experience with EDA tools from Synopsys… more
- Google (Mountain View, CA)
- … design will include analog mixed signal, radio frequency focused, and digital design for free-space optical communication links including; analog front-end, ... ASIC Lead Engineer, Project Taara (Fixed Term) Hardware...input from various teams, contribute to the detailed circuit design , own the foundry submission process, oversee physical… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
- Cisco (San Jose, CA)
- …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification, memory designs, and physical design ... and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology.… more
- Google (Mountain View, CA)
- …ensure functionality of the design . + Provide input on synthesis, timing closure, and Physical Design of digital blocks. + Take a leadership role on ... field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC DFT Technical Program Manager in San Jose, CA...and post silicon validation phases with additional exposure to physical design signoff activities. Who You Are… more
- Cisco (San Jose, CA)
- …strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. * Additionally, you'll develop ... accuracy. Who you'll work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture...refining design and timing constraints for seamless physical design closure. As part of this… more
- Google (Mountain View, CA)
- …Computer Architecture, Digital Design Verification, Digital Circuits, ASIC Physical Design , FPGAs, Embedded Systems, Memory Systems. Preferred ... + Experience with board layout (eg, working with CAD/PCB design ), Systems Integration, RF, Hardware Test, or Antenna. As...core Consumer Hardware products. The teams you work with design , develop, and deploy next generation consumer hardware while… more