- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and ... **Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on power /performance optimizations from SOC Architecture to… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... are expected to understand the design and implementation, develop power metrics and drive power reductions +...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- Qualcomm (San Jose, CA)
- …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design, optimize, verify, validate, implement, ... development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Meta (Menlo Park, CA)
- **Summary:** Meta Platforms Inc. is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. This organization is responsible for building ... expert engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Machine Learning Architecture (PhD) Responsibilities: 1.… more
- Cisco (San Jose, CA)
- …cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. What You'll Do You will contribute to developing ... of design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware...is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... chip development. + Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities +… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. Our servers and data centers are the foundation upon which ... to build "Green" data center accelerators. **Required Skills:** Machine Learning ASIC Engineer , Architecture Responsibilities: 1. Work on developing Data… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. Our servers and data centers are the foundation upon which ... our expert engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Architecture Responsibilities: 1. Work on advanced ASIC… more
- Cisco (San Jose, CA)
- …of the most complex ASICs being developed in the industry. What You'll Do As ASIC Verification Engineer in The Core Hardware Business Unit, you will be engaged ... Who You Are *Have a good understanding of the fundamentals of ASIC Design verification principles. *Ability to understand functional specifications outlined in… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our ... ASIC engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in Design… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Meta (Sunnyvale, CA)
- … engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Design Responsibilities: 1. Participate in Micro-architecture, ... **Summary:** Meta is seeking an ASIC Design Engineer Intern to join...of the IPs 3. Analyze designs and enhance PPA ( Power , Performance, Area) 4. Support and develop Verification Infrastructure,… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. What You'll Do * You...* Implement Verilog RTL to meet timing, performance, and power requirements * Contribute to full chip integration and… more
- Cisco (San Jose, CA)
- …Who You'll Work With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT, physical design, and post-silicon validation The ... a system company, so you can also use the ASIC to work with the System and Software teams...as a team, to develop innovative technology, and to power a more inclusive, digital future for everyone. How… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... physical design of an end-to-end IP or integration of ASIC /SoC design and point out lower power ...of ASIC /SoC design and point out lower power and higher performance trade-offs. 4. Define and implement… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....and generate optimized Gate Level Netlist for Timing, Area, Power . Debug the timing/area/congestion issues and work with RTL… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...System Verilog and HLS 4. Lint, CDC, Synthesis, & Power Optimization 5. Soft and hard IP identification, selection… more
- Qualcomm (Santa Clara, CA)
- …is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such… more