- Google (Sunnyvale, CA)
- …or PhD in Electrical Engineering or Computer Science. + 4 years of experience in digital/ ASIC design using SystemVerilog or RTL . + Experience in one or ... design architecture and microarchitecture specifications. + Develop SystemVerilog RTL to implement logic for ASIC /SoC products...(DV) teams to create testplans for, verify, and debug design RTL . + Work with physical … more
- Broadcom (San Jose, CA)
- …We are seeking for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining ... experience is a plus. + Experience in micro-architecture and RTL development. + Worked on architecture definitions on clocks,...in Tcl, Perl, Python scripting + Good understanding of ASIC design flow + Strong interpersonal skills… more
- Capgemini (San Francisco, CA)
- ** RTL Design Engineer ** **Location: San Jose CA...description:** . As an RTL Design Engineer you will be responsible for ASIC designs used ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic… more
- Meta (Sunnyvale, CA)
- …Area. 14. Knowledge of front-end and back-end ASIC tools. 15. Experience with RTL design using SystemVerilog or other HDL. 16. Experience managing multiple ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... and micro-architecture of digital subsystems + RTL design of digital circuits using Verilog...design of digital circuits using Verilog + Frontend design development and integration of large ASIC … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... & bus protocols, interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis… more
- Cisco (San Jose, CA)
- …Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using ... and review of code and functional coverage. * Ensure RTL quality with qualifying the design with...design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware… more
- Qualcomm (San Jose, CA)
- …a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design , optimize, verify, validate, implement, and document ... Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related...power use, and verification or similarly for custom circuit design /layout flow. * Utilizes tools/applications (eg, RTL … more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design … more
- NVIDIA (Santa Clara, CA)
- …Architecture, Computer Arithmetic, CMOS transistors and circuits is required. + Understanding of ASIC design flow including RTL design , verification, ... NVIDIA is seeking best-in-class ASIC Design Engineers to design...RTL , and deliver a fully verified, synthesis/timing clean design . + Support post-silicon validation activities. + Work with… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our...to improve performance and power. 5. Work with the RTL design team to understand partition architecture… more
- Qualcomm (Santa Clara, CA)
- …a closely related field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + ... closely related field + 5+ years of experience with ASIC design and verification tools, techniques, and...and methodology + 5+ years of experience with digital design concepts and RTL languages such as… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon ... engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Design Responsibilities:...Design , and Verification reviews and provide feedback 2. Design and develop RTL or HLS code… more
- Cisco (San Jose, CA)
- …the lab. Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... or Master's degree in Electrical or Computer engineering. * 8+ years of ASIC Design experience. * Excellent Verilog/System Verilog programming skills. *… more
- NVIDIA (Santa Clara, CA)
- …flow experience + Hold a basic sense of verification methodology + Good understanding of ASIC design flow including RTL design , verification, logic ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design ...for System-level modules (Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design , synthesis, timing + Silicon bring-up… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... development, executing from the inception of the design ( RTL or gate netlist) through the...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design … more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- Meta (Sunnyvale, CA)
- …data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL development using ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs,… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to ...Systems design . + A deep understanding of ASIC design flow including RTL ... be doing: + As a key member of our design team, you will be responsible for the micro-architecture...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more