• Design Verification

    Capgemini (San Francisco, CA)
    **Job Title: Design Verification Infrastructure Engineer ** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job Description:** **Key ... .Minimum 5 years of strong experience in EDA/CAD SoC/IP design verification and infrastructure development...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
    Capgemini (10/05/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...verification environments. 12. Experience in architecting and implementing Design Verification infrastructure and executing… more
    Meta (11/05/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...verification environments 11. Experience in architecting and implementing Design Verification infrastructure and executing… more
    Meta (10/18/24)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...verification environments. 13. Experience in architecting and implementing Design Verification infrastructure and executing… more
    Meta (10/18/24)
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  • Senior ASIC Verification

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High ... the cutting edge of industry techniques + Collaborate with architects, designers, verification engineers, as well as methodology and infrastructure engineers to… more
    NVIDIA (11/15/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1....verification environments. 12. Experience in architecting and implementing Design Verification infrastructure and executing… more
    Meta (11/13/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... and test cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and… more
    Meta (10/18/24)
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  • Design Verification Engineer

    SpaceX (Sunnyvale, CA)
    Design Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)...test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including… more
    SpaceX (11/01/24)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    **Summary:** As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your ... and test cases for multiple state of the art SOCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and… more
    Meta (10/18/24)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (Santa Clara, CA)
    **Job Title:** ** Design Verification Engineer ** **Job Location: Santa Clara CA** **Job description:** *Architect and Create verification environments ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_ **Location:** _CA-Santa… more
    Capgemini (09/14/24)
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  • Senior Digital Design Verification

    NVIDIA (Santa Clara, CA)
    We're now looking for a Senior Digital Design Verification Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA,...understanding the design and implementation, define the verification scope, develop the verification infrastructure more
    NVIDIA (10/12/24)
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  • ASIC Design Verification

    Google (Sunnyvale, CA)
    …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Verification Engineer you will use your ... design and verification experience to verify digital designs. You will collaborate...see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and… more
    Google (10/29/24)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (Sunnyvale, CA)
    …**Sunnyvale CA - Onsite role** **Job description:** We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_ **Location:** _CA-Sunnyvale_… more
    Capgemini (09/13/24)
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  • Senior Mixed-Signal Design

    NVIDIA (Santa Clara, CA)
    …sophisticated mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify ... We are looking for an Engineer to verify the design and...doing: + As a key member of our circuit verification team, you will verify the design more
    NVIDIA (10/25/24)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of Silicon One ... include: * Architect block, cluster and top-level DV environment infrastructure . * Develop DV infrastructure from scratch...other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC… more
    Cisco (10/01/24)
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  • Senior ASIC Design Verification

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... advanced verification tools, flows and methodologies. + Build and reform verification infrastructure and methodologies to meet the demands of next generation… more
    NVIDIA (09/25/24)
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  • ASIC Design Verification

    Google (Sunnyvale, CA)
    …Science, with an emphasis on computer architecture. + 4 years of experience in design verification . + Experience in Power aware verification , Gate level ... behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex...see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and… more
    Google (11/13/24)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers... verification engineers, designers, hardware and cross functional teams to… more
    Cisco (11/01/24)
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  • Design Verification Engineer

    Broadcom (San Jose, CA)
    …before you apply.** **Job Description:** Job duties: + Formal and functional verification of complex designs, especially around external interfacing IPs. + Identify ... designs that are suitable for formal verification , apply formal verification techniques and perform...sublayer)/Serdes designs. + Experience with external customer support for design IPs or VIPs. + Expertise in System Verilog… more
    Broadcom (11/06/24)
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  • ASIC Design Verification

    Broadcom (San Jose, CA)
    …power efficiency._** **_We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can ... teams to develop leading edge products. All aspects of Design Verification will be involved, along with...develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our… more
    Broadcom (11/06/24)
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