• IC CAD Engineer

    Power Integrations (San Jose, CA)
    In this position, you will be responsible for supporting all IC design CAD tools, which include but not limited to Cadence schematic entry, mixed mode circuit ... license management, user support, and vendor interface. You will also work with IC layout designers in taping out physical layout design to mask shop. Requirements:… more
    Power Integrations (09/20/24)
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  • ASIC Lead Engineer , Project Taara (Fixed…

    Google (Mountain View, CA)
    …+ Experience with CAD tool setup and debugging. + Familiarity with IC integration with photonics and related packaging technology. Ability to evaluate the impact ... ASIC Lead Engineer , Project Taara (Fixed Term) Hardware Engineering Mountain...design + Highly proficient in the use of standard IC design tools (Cadence Virtuoso, Innovus, etc.) and methodologies.… more
    Google (10/18/24)
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  • Principal Layout Engineer

    ManpowerGroup (San Jose, CA)
    Sr. Layout Engineer **SUMMARY:** A fast-growing Power Management division focusing on Power Loss Protection, PMICs, Motor Control, and Battery Management solutions ... and Industrial applications is seeking an experienced Principal Layout Engineer . **RESPONSIBILITIES:** + Layout of Power and Analog integrated...JI and SOI + Collaborate with Analog and Power IC design engineers in Asia and the US +… more
    ManpowerGroup (10/03/24)
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  • Sr. Semiconductor Modeling Engineer

    Siemens Digital Industries Software (Fremont, CA)
    …and high-performance computing. + Experience with PDE solvers and electromagnetics. + IC CAD experience (DRC, LVS, extraction, simulation). + Experience with ... design. We are looking for a highly motivated software engineer with solid semiconductor knowledge to work on the...on the Calibre engineering team in the Siemens EDA IC segment. You will be part of a team… more
    Siemens Digital Industries Software (10/25/24)
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  • Design Engineer Intern

    Cadence Design Systems, Inc. (San Jose, CA)
    …Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for next generation ... Requirements: The student intern should have completed foundational coursework in Digital IC design, Computer Architecture and VLSI design. Exposure to VLSI design… more
    Cadence Design Systems, Inc. (10/29/24)
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  • Senior Mixed-Signal ASIC Designer, Project Taara

    Google (Mountain View, CA)
    …Taara About the role: The Taara Project is seeking a Senior Integrated Circuit engineer leading the next generation circuit design as part of the R&D team developing ... design + Highly proficient in the use of standard IC design tools (Cadence Virtuoso, Innovus, etc.) and methodologies....analysis of analog or digital blocks. + Experience with CAD tool setup and debugging. + Experience in selecting… more
    Google (09/19/24)
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