- NVIDIA (Santa Clara, CA)
- We are now looking for a Power Architecture and Optimization Engineer - New College Grad! NVIDIA prides in having energy efficient products. We believe ... continued success. Our team is privileged to work on Power Optimization of Data center, gaming and...micro- architecture , RTL Design, methodology and AI based power optimization solutions. You will collaborate with… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA prides ourselves in having energy efficient products. We believe ... to fast-track Power anomaly detection. + Use AI to come up with Power optimization solutions. What We Need To See: + MS (or equivalent experience) with 3+… more
- Qualcomm (Santa Clara, CA)
- …+ 3 years of experience in low power micro- architecture , Design, Power Intent/Implementation, power optimization and power estimation + ... be working on WiFi (802.11x) technology, SOC Design, Low Power micro- architecture , Power Intent/Implementation, ... Intent; Power Implementation; WiFi or WLAN; Power Optimization ; ARM IP/Coresight based debug design… more
- Amazon (Sunnyvale, CA)
- …Amazon Dash, and Amazon Echo What will you help us create? The Role: As a Senior Power Engineer , you will be responsible for owning the power and energy ... consumption models, provide inputs to power architecture and conduct power consumption characterization on...and power distribution in embedded systems or power and energy consumption modelling and optimization … more
- NVIDIA (Santa Clara, CA)
- …impact role. We need a passionate, hard-working and creative individual to lead the power features all the way from architecture to delivering the features on ... product. What you'll be doing: + Architect next generation power management features and solutions, through system architecture...cases; identify opportunity and challenges in the area of power management and optimization to drive future… more
- Meta (Sunnyvale, CA)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and Design teams to assess ... level. We are looking for individuals with experience in power architecture definition and power ... Architecture , Design, DV, and Emulation teams for power flows, optimization and estimation **Minimum Qualifications:**… more
- NVIDIA (Santa Clara, CA)
- …and active power management. + Proven experience in system-level power optimization , including product binning, data analysis, and performance measurement. ... stems from ground breaking technology and outstanding talent. We are seeking a Senior Power Feature Design and BringUp Engineer to drive the development of… more
- NVIDIA (Santa Clara, CA)
- …stand out from the crowd: + Architecture and design experience in SoC software power management and optimization . + Prior experience in CPU and GPU DVFS, ... Senior System Software Engineer to join the GPU System Perf and Power Management Software team. The team oversees end-to-end Power Management solutions from… more
- NVIDIA (Santa Clara, CA)
- …in silicon power architecture , system level design, validation, and power /performance optimization . + Strong EE fundamentals on digital design, low ... and power based on roadmap. + Work closely with architecture , ASIC, board/platform design, software/firmware, marketing, and other cross-functional teams to… more
- Meta (Sunnyvale, CA)
- …cross-functional groups and vendors against plans. 15. Experience overall system power optimization and characterization or related experience. **Preferred ... multitask across various disciplines and tasks are a must. **Required Skills:** Power Electrical Engineer Responsibilities: 1. Responsible for creating power… more
- Google (Sunnyvale, CA)
- …delivering unparalleled performance, efficiency, and integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip ... . + Contribute to chip-package-system co-design by performing Signal Integrity (SI)/ Power Integrity (PI) analysis and optimization to involve in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... Signal Integrity solutions to complex system design problems. + Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D… more
- NVIDIA (Santa Clara, CA)
- …preferred. + Strong understanding of digital design, circuit analysis, algorithms, computer architecture , silicon speed and power , BIOS, drivers, and software ... product definition and specifications to help build and market the world's fastest power -shipping products. + You will design models and tools to automate and… more
- Qualcomm (Santa Clara, CA)
- …will own or participate in the following: * Performance exploration and power optimization opportunities. Explore high performance strategies working with the ... Timers, Interrupt controller, Configuration access protocols, RAS and safety aspects, AMU/PMU architecture , Power management architectures - Active and Idle … more
- NVIDIA (Santa Clara, CA)
- …Out From The Crowd: + Architecture and design experience in software power management and optimization . + Working experience in system software, operating ... We are now looking for a Senior System Software Engineer ! NVIDIA is searching for a world-class system software...GPU kernel drivers with a focus on performance and power ; and support the GPU architecture of… more
- Meta (Menlo Park, CA)
- …RTL development using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis, & Power Optimization 5. Soft and hard IP identification, selection and integration ... SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro- architecture… more
- Amazon (Cupertino, CA)
- …disciplines Software and Hardware engineers including but not limited to complier engineer , machine learning engineer , runtime engineer , performance ... ML Accelerators, and in storage with scalable NVMe. As an SDE ML Apps Engineer , you will work alongside Research Engineers and Applied Scientists to build backend… more
- Meta (Sunnyvale, CA)
- …constraints, UPF files, and other collateral for hand-off to physical design 6. Perform RTL power analysis and optimization to meet low power requirements 7. ... Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to...16. Familiarity with UVM methodology 17. Experience with low power design and optimization , including UPF 18.… more
- Meta (Sunnyvale, CA)
- …digital design skills to implement and contribute to the development and optimization of low power rendering hardware accelerators and state-of-the-art SoCs. ... **Summary:** Meta's mission is to give people the power to build community and bring the world...to look at the entire stack, from transistors, through architecture , firmware, and algorithms.We are growing our Graphics &… more
- Meta (Sunnyvale, CA)
- …your digital design skills to implement and contribute to the development and optimization of low power machine learning accelerators and state-of-the-art SoCs. ... **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital uArchitecture and...architecture 12. Knowledge of Physical Design and Low power implementation 13. Experience with Machine learning models, algorithms… more