• Senior DFT Methodology

    NVIDIA (Santa Clara, CA)
    …imagination and intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works on groundbreaking innovations involving crafting creative ... 3+, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (08/28/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …flows, and post-silicon test bring up procedures. Preferred qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow… more
    Cisco (10/17/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you ... + You will be responsible for all aspects of testing including methodology , logic insertion, verification, test pattern generation, test program bring-up, and… more
    NVIDIA (10/24/24)
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  • Senior Clocks Methodology

    NVIDIA (Santa Clara, CA)
    …to join us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In ... significantly. Modern clocking design needs to balance high frequency clocks with power, DFT , noise, circuit and physical design constraints. What you'll be doing: +… more
    NVIDIA (10/22/24)
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  • Sr. Physical Design Methodology

    Amazon (Cupertino, CA)
    …integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, ... flows for ML Accelerator chips in advanced nodes Drive improvement in RTL2GDS flows/ methodology for PPA and TAT improvements Create Dashboard and Central reports for… more
    Amazon (10/18/24)
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  • Senior Silicon Engineer PD CAD…

    Microsoft Corporation (Mountain View, CA)
    …+ Perform cross-functional decision making across UPF (Unified Power Format)/Low Power methodology /architecture, DFT methodology , Synthesis, Place and Route ... Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer ** to join our team!...end-users. + Excellent Communication skills across the board + DFT methodology and handling DFT more
    Microsoft Corporation (11/12/24)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing… more
    NVIDIA (09/20/24)
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  • Senior Staff Engineer , Electrical…

    Renesas (San Jose, CA)
    Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + ... Experience in digital design implementation including logical synthesis and DFT insertion with high coverage + Experience in static...+ Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in developing design… more
    Renesas (11/09/24)
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  • Senior Logic Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial ... intent. + Interface with architecture, physical design (PD), design for test ( DFT ), and other teams to optimize tradeoffs within the design. + Provide… more
    Microsoft Corporation (11/08/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and ... and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post silicon… more
    NVIDIA (11/15/24)
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  • Senior Board Test Engineer

    NVIDIA (Santa Clara, CA)
    We are looking to hire a Senior Board Test Engineer who will work in the Test Solutions Group at NVIDIA developing manufacturing GPU/CPU test solutions for Data ... + Investigate and introduce new manufacturing test technology and methodology to improve production efficiency. + Contribute to our...and validation infrastructure. + Review and provide feedback for DFT in the early design stages. + Debug complex… more
    NVIDIA (11/12/24)
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  • Senior ASIC Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... clock distribution and planning as well as impact of DFT logic in timing convergence. + Knowledge of circuits...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
    NVIDIA (09/27/24)
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  • Senior PCB Layout Engineer

    Google (Sunnyvale, CA)
    …OrCAD, Concept, Allegro. + Experience working with PCB design tools and methodology . Preferred qualifications: + Master's or PhD degree in Electrical Engineering, ... Proficiency with high-speed board design/layout. As a PCB Layout Engineer designer on the Platforms Infrastructure team, you will...use correct impedance rules, DFM and Design for Test ( DFT ) rule sets. + Work with hardware engineers, PCB… more
    Google (11/08/24)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with compute farm interaction: software deployment, performance… more
    NVIDIA (11/02/24)
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  • Sr. Silicon ATE Engineer , Project Kuiper

    Amazon (Sunnyvale, CA)
    …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more
    Amazon (11/14/24)
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  • Senior DFX Architect

    NVIDIA (Santa Clara, CA)
    …products, you will participate to drive major aspects of DFX architecture and methodology that will enable NVIDIA GPUs, custom processors and accelerators to excel ... (preferred) + Good exposure in multi-functional areas including RTL, DFT , clocks, performance and power. + Excellent analytical skills...are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
    NVIDIA (08/24/24)
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