• Senior Formal Verification

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for Formal Verification Engineer to help verify the design and implementation of industry's leading CPUs and other High Performance ... Computing Solutions. As a Formal Verification Engineer , you will play a key role in ensuring the functional correctness and completeness of our next… more
    NVIDIA (09/14/24)
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  • Senior ASIC Verification

    NVIDIA (Santa Clara, CA)
    The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... in industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage metrics, profiling tools, X prop, etc.… more
    NVIDIA (10/16/24)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    …Who You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of ... * Experience with Forwarding logic/Parsers/P4. * Experience with Veloce/Palladium/Zebu/HAPS. * Formal verification (iev/vc formal ) knowledge. * Domain… more
    Cisco (10/01/24)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Francisco, CA)
    **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding constraints...TCL or Perl or Python *Experience in Synthesis and Formal is a plus *Excellent verbal and written communication… more
    Capgemini (10/16/24)
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  • Senior ASIC Physical Design Engineer

    Capgemini (Santa Clara, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level + Understanding...or Perl or Python + Experience in Synthesis and Formal is a plus + Excellent verbal and written… more
    Capgemini (10/16/24)
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  • Senior Logic Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …Learning (ML) SoCs. + Working knowledge of writing assertions, coverage, and formal verification . + Effective communication skills, self-motivation, and ability ... and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in...Property (IP) + Silicon validation + Collaborate with the verification team to ensure the implementation meets both architectural… more
    Microsoft Corporation (11/08/24)
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  • Senior Staff Engineer , Electrical…

    Renesas (San Jose, CA)
    Senior Staff Engineer , Electrical Design Job...creation of place and route constraints + Experience in formal verification , lint and CDC/RDC checking + ... and high-speed design concepts + Participate in design, architecture, and verification reviews + Cover digital backend design from synthesis, static timing… more
    Renesas (11/09/24)
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  • Senior Silicon Engineer PD CAD…

    Microsoft Corporation (Mountain View, CA)
    …contributing to the future of Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer ** to join our team! If you are like tackling ... silicon engineering organization. **Responsibilities** + Establish Logical Equivalence Checking (LEC)/ Formal Equivalence Verification (FEV) methodology for hierarchical… more
    Microsoft Corporation (11/12/24)
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  • Senior Physical Design Engineer

    Broadcom (San Jose, CA)
    …to help through congestion resolution and timing closure. Should have experience of formal verification and timing analysis and Eco implementation. Should be ... manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate...implementation of blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. .… more
    Broadcom (11/01/24)
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  • Senior Hypervisor and RTOS Engineer

    NVIDIA (Santa Clara, CA)
    …of Automotive quality standards, ASPICE, ISO 26262, ISO 21434 + Hands-on experience with formal verification methods and tools, such as Ada/SPARK and TLA+ + ... world-class Autonomous Vehicles. We are making extensive use of formal methods to automate our workflow and increase the...SW. We are hiring now for the position of Senior System Software Engineer for Hypervisor and… more
    NVIDIA (10/24/24)
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  • Senior Digital Circuit Design…

    NVIDIA (Santa Clara, CA)
    …CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools + Have a strong background in Perl and ... We are now hiring for a Senior Logic and Digital Circuit Design Engineer...in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM + Proven experience with… more
    NVIDIA (10/30/24)
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  • Senior Software Engineer - RTL…

    NVIDIA (Santa Clara, CA)
    …modern C++, build systems, and database. + Experienced with EDA Vendor tools for design, verification and formal analysis. The base salary range is 148,000 USD - ... infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As...architectural, rtl, and gate level designs. As a software engineer , you will craft highly efficient software to automate… more
    NVIDIA (10/06/24)
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  • Senior Firmware Security Engineer

    NVIDIA (Santa Clara, CA)
    …threat models, attack-trees, static/dynamic analysis, fuzzing, and negative testing + Experience with formal verification + Passion for your work We are widely ... GPUs. We are searching for an outstanding security software engineer to fill an exciting, yet fun role on...are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
    NVIDIA (11/06/24)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …the world What You'll Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer /lead to engage in new development of our UCS ... Forwarding logic/Parsers/P4 * Prior experience with Veloce/Palladium/Zebu/HAPS * Prior experience with formal verification (iev/vc formal ) We Are Cisco… more
    Cisco (10/01/24)
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  • Physical Design Engineer , Annapurna Labs

    Amazon (Cupertino, CA)
    …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring… more
    Amazon (11/01/24)
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  • Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …ASIC physical design, and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level of expertise in PD ... of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring… more
    Amazon (10/18/24)
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