• Sr Principal Digital

    Cadence Design Systems, Inc. (San Jose, CA)
    …an impact on the world of technology. Provide technical support and customization of timing closure, analysis and ECO flows; spanning digital block, die and 3DIC ... proliferation of Cadence tools and technologies Requirements; 10+ years timing closure, analysis and ECO flows; spanning digital... timing closure, analysis and ECO flows; spanning digital block, die and 3DIC methodologies; for complex and… more
    Cadence Design Systems, Inc. (10/30/24)
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  • DSP or Serdes (Viterbi and encoder design) RTL…

    Cadence Design Systems, Inc. (San Jose, CA)
    …of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and ... developing flows at all phases of the digital design and functional verification. It is further expected...checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint… more
    Cadence Design Systems, Inc. (10/05/24)
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  • Sr . Staff Design Engineer (Low Power)

    Qualcomm (Santa Clara, CA)
    …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... WiFi or WLAN; Power Optimization; ARM IP/Coresight based debug design ** Principal Duties and Responsibilities:** * Leverages advanced ASIC knowledge and experience… more
    Qualcomm (10/10/24)
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  • Digital Design Engineer

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, adaptive filters . Working with… more
    Qualcomm (09/25/24)
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  • ASIC Digital Design Engineer - WiFi MAC

    Qualcomm (San Jose, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer, you will define, model, design, optimize,...flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for… more
    Qualcomm (09/23/24)
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