- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep ... understanding of timing constraints, including clock groups, exceptions, and clock exclusivity....scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... in coding- TCL, Python. Must have hands-on experience with NanoTime static timing analysis, its algorithms and associated circuit constraint checks. Should… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... TCL, Python. Must have hands-on experience with NanoTime static timing analysis, its algorithms and associated circuit constraint... timing analysis, its algorithms and associated circuit constraint checks. Ways to Stand Out From the Crowd:… more
- Broadcom (San Jose, CA)
- …debugging, and coverage closure + Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks ... design and validation techniques including UPF/CPF Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of fundamental physical ... design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with FPGA and/or emulation… more
- Broadcom (San Jose, CA)
- …from the marketing requirements and/or system requirements + prepare detailed design document, timing constraint file + RTL coding, Lint checks, CDC, Synthesis, ... Equivalency checking, STA, RTL/gate level simulations & silicon debug + Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc. + prepare block level resource requirements & development schedule +… more
- NVIDIA (Santa Clara, CA)
- …complete development of PCB layout, floor planning and detailed component placement, constraint management, with a concept of topology and signal/trace integrity. + ... a plus. + Knowledge of PCB design and consideration for layout, routing, and timing constraints, DFM, DFA, and DFT constraints in volume manufacturing is helpful. +… more