• Sr . SOC / ASIC

    SpaceX (Irvine, CA)
    Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL ...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $160,000.00 - $220,000.00/per year… more
    SpaceX (11/15/24)
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  • Sr . SOC / ASIC Timing…

    SpaceX (Irvine, CA)
    Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING SIGNOFF &...ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) + Analysis of clock domain crossing paths… more
    SpaceX (11/22/24)
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  • Sr . ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    Sr . ASIC Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
    SpaceX (11/16/24)
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  • Sr . DDR IP Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual ... Sr . DDR IP Design Engineer (Silicon Engineering) at...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
    SpaceX (10/21/24)
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  • Digital Integrated Circuit Design Engineer…

    The Boeing Company (Huntington Beach, CA)
    …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC /FPGA/ SoC design and verification - eg Synopsys VCS, Design ... external wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test) in house. SSED has… more
    The Boeing Company (12/12/24)
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  • Senior Security Firmware Engineer

    Western Digital (Irvine, CA)
    …teams in identifying and resolving issues. + Debugging, optimizing, and validating the Firmware on SoC platforms, as well as bringing up of FPGA and ASIC . + ... orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected… more
    Western Digital (11/16/24)
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