- Meta (Austin, TX)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...13. 3+ Years of experience as a Front End Synthesis & Integration Engineer 14. Experience with… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...16. Experience with SOC Design Integration & Front End Implementation 17. Experience with Front End Synthesis … more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...the DFT coverage for Stuck-at faults. 5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis , & Power Optimization 5. Soft and hard IP… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS. 3. Lint, CDC, Synthesis , & Power Optimization. 4. Soft and hard IP… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 6. Collaboration with implementation team to close the design on timing and… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 5. Collaboration with implementation team to close the design on timing and… more
- NVIDIA (Austin, TX)
- …make a lasting impact on the world. Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving ... + Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/ implementation flow, and design automation + Good understanding of SOC… more
- NVIDIA (Austin, TX)
- The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Verification Engineer interested in innovative approaches to drive design quality in our IP. This ... experience + Experience in pre-silicon verification (UVM, SystemVerilog), System-On-Chip design/ implementation flow, and design automation + Strong coding skills in… more
- Amazon (Austin, TX)
- …RTL - Ensure quality by running and tracking results of front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon ... - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is committed to a diverse and inclusive workplace. Amazon is… more
- Amazon (Austin, TX)
- …low power design & the impact of DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification including test plan ... years of experience in digital design, preferably in SoC design and implementation Preferred Qualifications Master's or Ph.D degree in Electrical / Communications… more
- Qualcomm (Austin, TX)
- …to help create a smarter, connected future for all. QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions ... SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and...also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance,… more
- Meta (Austin, TX)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
- BAE Systems (Austin, TX)
- **Job Description** BAE Systems has an open position for a Senior FPGA Digital Design Engineer ! See what you re missing. Our employees work on the world s most ... Group is looking for a Senior FPGA Digital Design Engineer to support FPGA designs through all phases of...including assisting in design architecture, ownership of RTL coding, synthesis , place and route, timing closure, basic test bench… more
- BAE Systems (Austin, TX)
- **Job Description** BAE Systems is seeking a Senior Principal FPGA Design Engineer ! See what you re missing. Our employees work on the world s most advanced ... Group is looking for a Senior Principal FPGA Design Engineer to support FPGA designs through all phases of...requirements generation and design architecture, ownership of RTL coding, synthesis , place and route, timing closure, basic test bench… more